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HTR 80 MHz 40 ps 100 ppm RJ-45 ( pinning std RG568B ) 2.5V-CMOS

Clock requirements. Board Freq. Jitter (p-p) Freq. tolerance Connector Level. HTR 80 MHz 40 ps 100 ppm RJ-45 ( pinning std RG568B ) 2.5V-CMOS. HTR 40 MHz - 0 RJ-45 ( pinning std RG568B ) TTCrx output. HEX-SLB 40 MHz 100 ps 0 VME P2 con. Dif. LVPECL .

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HTR 80 MHz 40 ps 100 ppm RJ-45 ( pinning std RG568B ) 2.5V-CMOS

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  1. Clock requirements Board Freq. Jitter (p-p) Freq. tolerance Connector Level HTR 80 MHz 40 ps 100 ppm RJ-45 (pinning std RG568B) 2.5V-CMOS HTR 40 MHz - 0 RJ-45 (pinning std RG568B) TTCrx output HEX-SLB 40 MHz 100 ps 0 VME P2 con. Dif. LVPECL

  2. TTCrx chip (VDD=3.3V VCC=5V) IN IN_b Ck Ck Ck/2 HTR clock scheme L1A_LEMO VME J2 CK_LEMO To other devices .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. TTC_CLK40 RJ-45 Cat5 AMP 558342-1 TTC LVDS DS90LV001 .. .. .. .. SpareOut RX_BC0 LVDS DS90LV001 PCK953 LVPECL- to-LVTTL p-p~3 ps 8 clocks to TLKs 1 ck to Xilinx 3.3V-PECL 80 MHz CLK MC100LVEL37 PCK953 LVPECL- LVTTL p-p~3 ps 8 clocks to TLKs 1 ck to Xilinx p-p~2 ps 80 MHz Differential 3.3V-PECL Xtal RX_CLK 3.3V PECL 40 MHz (On final design path separate from Xtal)

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