Performed by:Itzik Adzashvili Akiva Megrlashvili Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט (סופי) Subject: Project name Performed by:Itzik Adzashvili Akiva Megrlashvili Instructor: Mony Orbach סמסטר (חורף/אביב) תשס"א 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract In last decades uprising using of video processing raised the needed of converting analog video from camera to digital Stream. The sample card aim is convert analog video to digital video stream and transmit the video data to processing system and present it to camera in high quality. The second challenge of this card to transmit the video data of rate 10MHz –25MHz . 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description Sample analog video signal Y COMPOSITE convert to digital desire format: RGB 16 bit YUV 16 bit Transmit the stream to ATM by using parallel protocol- UTOPIA. The rate of sample is in Pixel clk 15Mhz. The second card was built to debug the sample card , First is implemented UTOPIA handshake to transmit unit Second convert the digital video to analog video signal SVGA And to interface to monitor 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Hardware • A/D converter -BT 812 • UTOPIA handshake implemented by FPGA 10k20 (altera) • D\A converter –saa7167 (philips) 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram MPU UTOPIA FRAME UTOPIA handshake ALTERA Bt init FIFO ANLOG VIDEO A/D Bt812 DATA ANTI ANAL FILTER RGB/YUV 5

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram UTOPIA Handshake ALTERA DAC I2C PHILIPS MPU DIGITAL VIDEO UTOPIA FRAME FIFO H sync DATA V sync 6

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram Reset_fifo Power_up reset Reset_Bt [7:0]D Bt_init Mpu_buffer wr Utopia_handshake R_soc Rclk Renb Fifo_EMPTY _ FIFO READ ENBLE R_CLAV 24 16 Video_in RGB/YUV 16<-24 VID_MUX clk

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram R_SOC UTOPIA CONTROLER R_ENB R_CLAV R_CLK FIFO_WRITE_ENB FIFO FULL I2C MASTER SCL SDA