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A 1-GS/S 6-BIT FLASH ADC IN 90 NM CMOS

A 1-GS/S 6-BIT FLASH ADC IN 90 NM CMOS. Adviser : Dr.Hsun-hsiang Chen Presenter : Chieh-En Lo 97662004. REFERENCE. Shaker, Mohamed O.; Gosh, Soumik; Bayoumi,

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A 1-GS/S 6-BIT FLASH ADC IN 90 NM CMOS

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  1. A 1-GS/S 6-BIT FLASH ADC IN 90 NM CMOS Adviser : Dr.Hsun-hsiang Chen Presenter : Chieh-En Lo 97662004

  2. REFERENCE Shaker, Mohamed O.; Gosh, Soumik; Bayoumi, Magdy A.;Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on2-5 Aug. 2009 Page(s):144 - 147 Digital Object Identifier 10.1109/MWSCAS.2009.5236133

  3. OUTLINE • INTRODUCTION • FLASH ARCHITECTURE • PROPOSED 6-BIT FLASH ADC • SIMULATION RESULTS • CONCLUSION

  4. INTRODUCTION • We present a new low power 6-bit flash ADC which uses minimum number of comparator. • The new design uses 10comparators and 9 multiplexers while the traditional one uses 63 comparators. • The main concern of this paper is to reduce the power consumption for flash ADC to be suitable for usage in low voltage application.

  5. FLASH ARCHITECTURE

  6. PROPOSED 6-BIT FLASH ADC (1/4)

  7. (2/4)

  8. (3/4) Vclk =0 Vin > Vref Vout = 1 Vin < Vref Vout = 0 1 1 0 1 0 1 0 0 0

  9. Vclk = 1 Vin > Vref latch 1 0 1 0 0 0 1 0 0

  10. (4/4)

  11. SIMULATION RESULTS

  12. CONCLUSION • In this paper, the design and the simulation results of a low-voltage 6-bit CMOS ADC has been presented. The maximum sampling speed is 1 GHz and the analog supply voltage is only 1.2 V. This architecture can be extended to high resolution applications because of the simplicity of the circuit.

  13. THE END

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