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Spice Model of HY5DU121622ATP

Spice Model of HY5DU121622ATP. 27 Aug. 2004 Memory R&D. Semiconductor. File Included. Tech. Files Model Parameter : typ.inc, min.inc, max.inc Package model : 66tsop.lib Dout Strength Control : mode_control.lib cmd/addr input buffer netlist / sample input deck

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Spice Model of HY5DU121622ATP

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  1. Spice Model ofHY5DU121622ATP 27 Aug. 2004 Memory R&D Semiconductor

  2. File Included • Tech. Files • Model Parameter : typ.inc, min.inc, max.inc • Package model : 66tsop.lib • Dout Strength Control : mode_control.lib • cmd/addr input buffer netlist / sample input deck • SCH_CA.inc / 512DDR_ca.sp • clk input buffer netlist / sample input deck • SCH_CLK.inc / 512DDR_clk.sp • dm input buffer netlist / sample input deck • SCH_DM.inc / 512DDR_dm.sp • dq output buffer netlist / sample input deck • SCH_DQ.inc / 512DDR_dq.sp

  3. Checking Compatibility • Extract files from ‘HY5DU121622ATP_spice.zip’ under any directory where the simulation would be executed. • Run a simulation with ‘512DDR_ca.sp’ as the input deck for cmd/addr buffer. • Run a simulation with ‘512DDR_clk.sp’ as the input deck for clock input buffer. • Run a simulation with ‘512DDR_dm.sp’ as the input deck for dm input buffer. • Run a simulation with ‘512DDR_dq.sp’ as the input deck for data in/out buffer. • If you could see the same result as the one seen on page 8 of this material, our model would be compatible with your simulation environment.

  4. Schematic (Cmd/Addr. Buffer) Control pin Input buffer Enable : EN (High active) Cmd/Addr. Input : CA Reference voltage : VREF Output of Input Buffer : CA_OUT

  5. Schematic (CLK Buffer) Control pin Input buffer Enable : EN (High active) Differential CLK Input : CLK/CLKB Reference voltage : VREF Output of CLK Buffer : CLK_OUT

  6. Schematic (DM Buffer) Control pin Input buffer Enable : EN (High active) DM Input : DM Reference voltage : VREF Output of DM Buffer : DM_OUT

  7. Schematic (DQ Buffer) Data Input Control Pin Input buffer Enable : EN (High active) Data Input : DIO Reference voltage : VREF Output of DM Buffer : DM_OUT Data Output Control Pin Output buffer Hi-Z Enable : OUTOFF Rising Edge Data : RDO Falling Edge Data : FDO Rising Data Out enable : RCLK Falling Data Out enable : FCLK Mode Control strength Strength WEAK 50% FULL 100%

  8. Sample Simulation Results CLK Hspice 512DDR_clk.sp Package : 66pin TSOP-II Condition : typical case VREF=1.25V CLKB OUT Hspice 512DDR_dq.sp Package : 66pin TSOP-II Condition : typical case Mode control : FULL VREF=1.25V RCLK FCLK OUTOFF DIO

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