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ECE243

ECE243. CPU. IMPLEMENTING A SIMPLE CPU. How are machine instructions implemented? What components are there? How are they connected and controlled?. MINI ISA:. every instruction is 1-byte wide data and address values are also 1-byte wide address space

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ECE243

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  1. ECE243 CPU

  2. IMPLEMENTING A SIMPLE CPU • How are machine instructions implemented? • What components are there? • How are they connected and controlled?

  3. MINI ISA: • every instruction is 1-byte wide • data and address values are also 1-byte wide • address space • byte addressable (every byte has an address) • 8 addr bits => 256 byte locations • 4 registers: • k0..k3 • PC (resets to $80) • Condition codes: • Z (zero), N (negative) • these are used by branches

  4. Some Definitions: • IMM3: a 3-bit signed immediate, 2 parts: • 1 sign bit: sign(IMM3) • 2 bit value: value(IMM3) • IMM4: a 4-bit signed immediate • IMM5: a 5-bit unsigned immediate • R1, R2: registers variables • represent one of k0..k3 • SE8(X): • means sign-extend value X to 8 bits • NOTE: ALL INSTS DO THIS LAST: • PC = PC + 1

  5. Mini ISA Instructions load R1 (R2): R1 = mem[R2]   PC = PC + 1 store R1 (R2): mem[R2] = R1   PC = PC + 1 add R1 R2 R1 = R1+ R2 IF (R1 == 0) Z = 1 ELSE Z = 0 IF (R1< 0) N = 1 ELSE N = 0   PC = PC + 1 sub R1 R2 R1= R1 - R2 IF (R1 == 0) Z = 1 ELSE Z = 0 IF (R1< 0) N = 1 ELSE N = 0 PC = PC + 1

  6. Mini ISA Instructions nand R1 R2 R1= R1 bitwise-NAND R2 IF (R1 == 0) Z = 1 ELSE Z = 0 IF (R1< 0) N = 1 ELSE N = 0    PC = PC + 1 ori IMM5 K1 = K1 bitwise-OR IMM5 IF (R1 == 0) Z = 1 ELSE Z = 0 IF (R1< 0) N = 1 ELSE N = 0   PC = PC + 1 shift R1 IMM3 IF (sign(IMM3)) R1 =R1 << value(IMM3) ELSE R1 = R1 >> value(IMM3) IF (R1 == 0) Z = 1 ELSE Z = 0 IF (R1< 0) N = 1 ELSE N = 0   PC = PC + 1

  7. Mini ISA Instructions bz IMM4 IF (Z == 1) PC = PC + SE8(IMM4)     PC = PC + 1 bnz IMM4 IF (Z == 0) PC = PC + SE8(IMM4)     PC = PC + 1 bpz IMM4 IF (N == 0) PC= PC + SE8(IMM4)    PC = PC + 1

  8. ENCODINGS: Inst(opcode) • Load(0000), store(0010), add(0100), sub(0110), nand(1000): • Ori: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

  9. ENCODINGS: Inst(opcode) • Shift: • BZ(0101), BNZ(1001), BPZ(1101): 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

  10. DESIGNING A CPU • Two main components: • datapath and control • datapath: • registers, functional units, muxes, wires • must be able to perform all steps of every inst • control: • a finite state machine (FSM) • commands the datapath • performs: fetch, decode, read, execute, write, get next inst

  11. ECE243 CPU: basic components

  12. REGISTERS REGWrite? out in REG clock 8 8 • REGISTERS • can always read • we assume falling-edge-triggered • in is stored if REGWrite=1 on falling clock edge • we won’t normally draw the clock input

  13. MUXES out 0 1 8 8 8 select • ‘select’ signal chooses which input to route to output

  14. REGISTER FILE 2 2 2 8 8 REGWrite? R1 Out1 Reg FILE (k0,k1,k2,k3) Out2 R2 in Rwrite clock 8 • Out1 is the value of reg indexed by R1 • Out2 is the value of reg indexed by R2 • if REGWrite is 1 when clock goes low • then the value on ‘in’ is written to reg indexed by Rwrite

  15. ALU (arithmetic logic unit) 8 8 8 Z N In0 out In1 3 ALUop • ALUop: • add = 000 • sub = 001 • or = 010 • nand = 011 • shift = 100 • Z = nor(out7,out6,out5…out0) • N = out bit 7 (implies negative---sign bit)

  16. MEMORY • our CPU has two memories for simplicity: • instruction memory and data memory • known as a “Harvard architecture”

  17. INSTRUCTION MEM INST MEM addr Iout 8 8 • is read only • Iout is set to the value indexed by the address

  18. DATA MEMORY 8 8 8 MEMRead? MEMWrite? DATA MEM addr clock Din Dout • can read or write • but only one in a given clock cycle • on falling clock edge: • if MEMWrite==1: value on Din is stored at addr • if MEMRead==1: value at addr is output on Dout

  19. SE8(x): SIGN-EXTEND TO 8 BITS I3 O3 O7 I2 O2 O6 I1 O1 O5 I0 O0 O4 • assuming 4-bit input • Recall: want: • SE8(0100) -> 00000100 • SE8(1100) -> 11111100 • In bits i3,i2,i1,i0; out bits o7…o0

  20. ZE8(x): ZERO EXTEND TO 8 bits O3 O7 O2 O6 0 O1 O5 I4 O0 O4 I3 I2 I1 I0 • assuming 5-bit input • Recall: want • ZE8(00100) -> 00000100 • ZE8(11100) -> 00011100 • In bits i4,i3,i2,i1,i0; out bits o7…o0

  21. ECE243 CPU: Single Cycle Implementation

  22. SINGLE CYCLE DATAPATH Inst1 Inst2 1 cyc • each instruction executes entirely • in one cycle of the cpu clock • registers are triggered by the falling edge • new values begin propagating through datapath • some values may be temporarily incorrect • the clock period is large enough to ensure: • that all values correct before next falling edge

  23. FETCH 8 8 • needed by every instruction • i.e., every instruction must be fetched addr PC INST MEM inst PCwrite?

  24. PC = PC + 1 8 8 PC INST MEM addr inst PCwrite?

  25. BRANCHES: BZ IMM4 8 8 8 7 6 5 4 3 2 1 0 IMM4 opcode • (if branch is taken does: PC = PC + IMM4 + 1) PC INST MEM addr inst PCwrite? + 1

  26. ADD add R1 R2 0 1 1 + + 8 8 8 4 8 i7 i6 i5 i4 i3 i2 i1 i0 R2 0 1 0 0 R1 SE8 Inst: • does r1 = r1 + r2 • same datapath for sub and nand PC INST MEM addr inst PCwrite? PCsel IMM4

  27. SHIFT: SHIFT R1 IMM3 i7 i6 i5 i4 i3 i2 i1 i0 0 1 IMM3 R1 0 1 1 N 1 Z + + 2 2 8 2 4 8 8 8 SE8 R2 2 REGwrite? REG FILE Rw Out1 PC A L U INST MEM addr R1 Out2 inst PCwrite? in PCsel IMM4 ALUop

  28. ORI: ORI IMM5 0 1 N 1 Z + A L U + 2 8 8 8 8 8 4 2 SE8 i7 i6 i5 i4 i3 i2 i1 i0 IMM5 1 1 1 R2 2 • does: k1 <- k1 bitwise-or IMM5 REGwrite? REG FILE Rw Out1 PC INST MEM addr R1 Out2 inst PCwrite? in PCsel ZE8 IMM3 IMM4 ALUop ALU2

  29. Store: Store R1 (R2) 0 1 1 0 N 1 Z 5 3 00 + + A L U 01 10 11 2 2 8 8 8 4 2 8 8 2 i7 i6 i5 i4 i3 i2 i1 i0 R2 opcode R1 SE8 R2 2 Inst: • does: mem[r2] = r1 R1sel REGwrite? 1 REG FILE Rw Out1 PC INST MEM addr R1 Out2 inst PCwrite? in ZE8 IMM5 PCsel ZE8 IMM3 IMM4 ALUop ALU2

  30. Load: Load R1 (R2) 0 1 1 0 N 1 Z 3 5 00 + A L U + 01 10 11 8 4 8 2 2 8 8 2 2 8 i7 i6 i5 i4 i3 i2 i1 i0 R2 opcode R1 SE8 R2 2 Inst: • does: r1 = mem[r2] MEMwrite MEMread addr Data MEM R1sel REGwrite? Din 1 REG FILE Rw Out1 PC INST MEM addr R1 Out2 inst PCwrite? in ZE8 IMM5 PCsel ZE8 IMM3 IMM4 ALUop ALU2

  31. Final Datapath! 0 1 1 0 1 0 N 1 Z 5 3 00 A L U + + 01 10 11 8 8 8 2 4 2 2 8 8 2 SE8 R2 2 MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 REG FILE Rw Out1 PC INST MEM addr R1 Out2 inst PCwrite? in ZE8 IMM5 PCsel ZE8 IMM3 IMM4 ALUop ALU2

  32. DESIGNING THE CONTROL UNIT opcode PCsel … CTRL Z N • CONTROL SIGNALS TO GENERATE: • PCsel, PCwrite, REGwrite, MEMread, MEMwrite, R1sel, ALUop, ALU2, RFin

  33. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 load R1 (R2)

  34. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 store R1 (R2)

  35. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 add R1 R2

  36. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 sub R1 R2

  37. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 nand R1 R2

  38. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 ori IMM5

  39. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 shift R1 IMM3

  40. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 bz IMM4

  41. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 bnz IMM4

  42. Control Signals MEMwrite MEMread addr Data MEM R1sel REGwrite? RFin Din 1 1 REG FILE Rw Out1 PC INST MEM addr 0 R1 Out2 inst PCwrite? in 0 1 ZE8 IMM5 PCsel 1 0 ZE8 IMM3 IMM4 ALUop ALU2 N 1 Z 3 5 00 + + A L U 01 10 11 2 2 8 2 8 2 8 8 8 4 SE8 R2 2 bpz IMM4

  43. All Control Signals

  44. All Control Signals

  45. Building Control Logic: MemRead

  46. Building Control Logic: PCSel

  47. ECE243 CPU: Multicycle Implementation

  48. A Multicycle Datapath

  49. Key Difference #1: Only 1 Memory

  50. Key Difference #2: Only 1 ALU

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