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High End Computing

High End Computing. Graphics Hardware and Software Architectures. Presentation Overview. Short History Today High End Computer Architecture Specialized Graphics Hardware Software Architecture Instantiated. Short History. Federally sponsored University research began in 1965

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High End Computing

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  1. High End Computing Graphics Hardware and Software Architectures

  2. Presentation Overview • Short History • Today • High End Computer Architecture • Specialized Graphics Hardware • Software Architecture Instantiated

  3. Short History • Federally sponsored University research began in 1965 • Ivan Sutherland and Jim Clark • New technologies make graphics accessible • VLSI chips • High Level Programming Languages • Less expensive HW led to growing market • Jim Clark developed Geometry Engine • Founded SGI (Silicon Graphics Inc.)

  4. Today • SGI is an industry leader • High Performance Graphics Computer Development • Our Example: Onyx2 InfiniteReality2 • Designed to provide system support for OpenGL

  5. High End Computer ArchitectureOnyx2 InfiniteReality2 • ccNUMA (Cache Coherent Non Uniform Memory Access) Architecture • Automatic scaling of system and graphics bandwidth • Low transport latency • Continuous, real-time fly-overs of large terrain • Support interactive, immersive visualization of unbounded volumes (Visible Human)

  6. Midplane Node XIO XIO Node Node Node Router Router Node Mid- plane Mid- plane Mid- plane Node Node Node Router Router Node XIO XIO Node Midplane Onyx2 InfiniteReality2 cont. XIO XIO XIO Router Router Router Interconnection fabric Router XIO Router Router XIO XIO ccNUMA Diagram

  7. RAM RAM R10000 R10000 R10000 MIDPLANE R10000 R10000 R10000 I/O C R O S S B O W HUB HUB XIO Graphics Node DMEM DMEM Router PCI Mid- plane R10000 I/O Cards Node R10000 Router XIO Onyx2 InfiniteReality2 cont. Graphics

  8. MIDPLANE I/O C R O S S B O W Graphics Graphics Pipeline PCI Geometry Board I/O Cards Raster Manager Display Generator Graphics Hardware

  9. Graphics Pipeline • Supports primitives • Polygons • Vectors • Points • Parametric polynomial surfaces • Primitives combine • Mesh polygon strips with common vertices

  10. GE16 Data Management Pixels Textures Video Geometry Processor Transformations Lighting Clipping Projection Host Interface Processor Geometry Distributor Geometry Engine (GE16) Geometry Engine (GE16) Geometry Engine (GE16) Geometry Engine (GE16) Geometry – Raster FIFO Geometry Board Crossbow GeometryBoard

  11. RM9 Vertex Bus Fragment Generator Pixels Texels Texture Memory Raster Manager Fragment Processing 80 Image Engines Frame buffer Raster Memory (RM9) Raster Memory (RM9) Raster Memory (RM9) Raster Memory (RM9) Raster Manager

  12. De-interleaver Display Channel DAC ENC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC Display Generator

  13. Cosmic Head http://www.realshades.com/3D/gallery/3D-001.html

  14. Software ArchitectureOpenGL • Multi-platform industry standard graphics library • A state machine • Native graphics programming interface for Onyx2 InfiniteReality2 • Implemented within graphics subsystem

  15. Fragment Generator Fragment Generator Fragment Generator Fragment Generator Texture Memory Texture Memory Texture Memory Texture Memory Feedback selection Geometry Data Command Tokens to Display Lists Pixel Data Vertex Bus RM9 RM9 RM9 RM9 HIP Image Engines Image Engines Image Engines Image Engines Geometry Distributor GE16 GE16 Frame buffer Frame buffer Frame buffer Frame buffer GE16 GE16 Display Channel ENC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC Display Channel DAC FIFO De-interleaver Fragment Operations Unpack Vertices Unpack / Pack Pixels Texture Memory Operations Point, Line, Polygon Rasterization Image Rasterization Frame buffer Vertex Operations Pixel Operations

  16. Feedback Selection Unpack Vertices Vertex Operations Point, Line, And Polygon Rasterization Geometry Fragment Operations Display Lists Texture Memory Command Tokens FB Unpack/ Pack Pixels Pixel Operations Image Rasterization Pixels Software Architecture Mapped Over Hardware Architecture Geom. Dist. Frag. Gen. Fragment Processing HIP GE16 TMEM Frame buffer

  17. Some Specifications of Onyx2 Infinite Reality2 • Two or four 4MB cache MIPS R10000 processors • 128MB to 8GB of memory • Single graphics pipeline with one or two Raster Managers • 64MB of texture memory • Up to 160MB of frame buffer capacity

  18. Mips R10000 • This processor features a four-way superscalar RISC processor that • fetches and decodes four instructions per cycle, • speculatively executes beyond branches, with a four-entry branch stack, • uses dynamic out-of-order execution, • implements register renaming using map tables, and • achieves in-order graduation for precise exceptions.

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