TDC rate tests

1. TDC rate tests Stefano Venditti – Universityof Pisa & INFN NA62 Collaboration meeting – TDAQ workinggroup – 08/02/2012

2. Outline • Characteristics and limitationsof the HPTDC architecture • Constant rate tests • Closesignaltests • L1 buffer tests • Conclusions

3. HPTDC – Features and limitations • TDC used in continuoustriggering mode: trigger windows must cover the wholetimewindow • 4 word-deepderandomizerforeachchannel (before the L1 FIFO). If a word (leading or trailing) isproducedbyTDCswhilethisfifois full, the word isLOST and no error word isproducedbyTDCs • L1 256 word-deep FIFO for a groupof 8 channels (4 L1 FIFO/TDC). Words stay hereuntil a trigger isprocessed.If the FIFO is full the word isLOST and anerror word iswritteninto the readout FIFO • Wordstobemovedto the readout FIFO or eliminated are chosenaccordingtoparameters set in the TDC configuration (named TROFF, MAWIN and REJOF in TDSPY) • TDC PARAMETERS WHICH MIGHT HELP • TRIGGER FREQUENCY: bydecreasing the trigger interval (usually set at 12.8/i.e. rollover/4) the L1 FIFO occupancyshoulddecrease • TDC CORE CLOCK: using the TDC’s internallogic at 80 MHz shoulddecrease the FIFO occupancy (especially the 4 word-deepone)

4. Some newfeatures • External clock fedinto the pattern generatorthroughanexternal probe: the same clock usedfor the TEL1 can beusedto generate patterns • Patternshitting the samebinsof the TDC roll-over (apartfromresolutioneffects) can beproduced, ifrolloveris a multiple of the pattern length • A timeorderinghasbeenintroduced in Giuseppe’s acquisitionprogram (see last meeting’s talk), allowingfor some data analysisimrpovements • A simple software random pattern generatorhasbeenwritten: randompatternsfor the PG are createdinto a propertxt format (through a perl script) and thenloadedinto the PG. Signalssyncronousto the TDC clock can “probe” itsinternallogic

5. Periodic pattern, single channel Patternshaving the samelengthof a trigger period (12.8 µs, 512 steps) were sent tothe TDCs at increasingrates(i.e. increasingsignals/pattern (S/P) ratio, a PG signal can beas short as a clock cycle), signalshave the maximumpossiblespacingbetweenthem. Es: (1 signal/512)*40 MHz ~ 80 KHz • Scanfrom 1/512 S/P (~80 KHz) to 1/8 S/P (5 MHz) • L1 overflow @ 5 MHz, togetherwith word repetitions & timestamps/counterslost. • Lossescorrelatedwithtriggers • However the numberofwords/trigger ((512/8)*2=64) shouldnotfill the L1 buffer • Possibleexplanation: the emptyingof the L1 FIFO (whichis NOT a real FIFO!) takes some clock cycles, when the rate istoo high thiscannotbedoneefficiently • The situation doesnotimproveif trigger periodisreduced (in principleitshould) SIGNALS LOST: MODULATION WITHIN TRIGGER WINDOW ALL SIGNALS COLLECTED LEAD+TRAIL 25 ns DISTANCE

6. Periodic pattern - 8 channels,same L1 FIFO 8 channelssharing the same L1 FIFO werepulsedwithpatternsofincreasing rate. Maximizationof the distancebetween the pulsesover the 12.8 µs trigger time 40 MHz TDC core clock • Althoughproblemsin the firmware are stillpresent at higherrates, the >500 KHz rate/channelseemsto hit on the L1 overflowproblem, whichmightbe a limitationof the TDC itself • A similarmeasurementwith 80 MHz TDC core clock doesnotyield L1 overflows (althoughrepetitions are present), which are seenonly at >1 MHz/channelrates • Ifthiswillbeconfirmedbyfurthertests, the maximum rate/channelusingall the 8 channelfromone L1 FIFO isprobablylimitedto~ 1 MHz

7. Istantaneous rate PG logicworking @ TDC clock allowstomeasurehowquickly the 4 word-deepFIFOs are emptied (i.e., howmany clock cyclesittakes. 12.8 µs, x10K • STRATEGY • A packetof N closelyspacedsignalsis sent to the TDC. • A largetimeinterval (trigger period) is set before the followingpacketis sent. Thisallowstodisentangle the emptyingof 4-words FIFOsfrompossible L1/firmwareproblems • If the acquisitionis 100% efficient, numberofsignalsincreasedby 1 unit • Ifleadings/trailings are lost, spacingbetweensignalsincreasedby 1 unit • Measurementsperformedfor 40 MHz and 80 MHz TDC core clock allwords collected wordslost 80 MHz 25 ns 40 MHz 80 MHz core clock seemstobemuchbetterforchannel FIFO’s occupancy.

8. Asyncronoussignals • The test performedforsyncronoussignalshavebeenrepeatedin the asyncronous case, with PG clock rangingfrom 20 to 100 MHz and variablerates . • A presenceof word repetitions/lossesisdetected, whichincreases at increasingrates • No L1 errors are seen up toratessimilartothosewere L1’s show up whenthe PG signalsaresynchronous Thispointsagainto a problem in the firmware. Randompatternshavebeenproduced and are readytobetested. Howeverthesetestswillbedoneonlywhentheseproblemswillbeunderstoodand solved (hopefullybynext meeting)

9. Conclusions • The problemsseen in the rate testsbelongto at leasttwodifferentcauses (whichmightbesomehowcorrelated): • A L1 FIFO abnormally full: thismightbe due eithertoarchitecturelimitations (no way out) or towrong TDC settings(trigger windows?). • A firmwareproblemshowing at high rates, probably due to TDC/TDCB synchronization. We’lltryto cure itin the nextdays (signaltapwillbeneeded) • The 80 MHz featureseemstoprovidesizableimprovements, butitseffectcan befullyevaluatedonlyafter the twoafore-mentionedproblemswillbeunderstood • Tests on randomsignalsofincreasingaveragerates (on single channel and L1 groups) are readytobeperformed • Whenusing 8 channelssharingthe same L1 FIFO, averagerateshigherthan~1 MHz/channelare probablyunsustainable