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Ethernet

Learn about interfacing with an Ethernet PHY, control status, addressing, and the MAC layer in Ethernet networking. Includes detailed diagrams and explanations.

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Ethernet

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  1. Ethernet Ethernet Controller How do you interface with an Ethernet PHY? 1-1

  2. Control Status Tx 110 Control State Machine 10BT To/From PHY 10/100 MAC M I I Tx FIFO (128b) Address Filtering/ Statistics Rx FIFO (2048b) Rx 110 EFE module DMA Controller MAC module Ethernet Controller Block Diagram 1-2

  3. Ethernet MAC-PHY Media-Independent Interface (MII) MDIO Net+ARM MAC PHY PHY Mgt (e.g., setup) MDCLK TXD Tx Data TXEN “Data Ready” RXDV TXER Tx/Rx Error RXER TXCLK Clocks for Tx/Rx RXCLK Rx Data RXD CRS Carrier Sense Collision COL (Remainder of MII pins are V or GND.) 1-3

  4. PHY Management • Software sends/receives a serial stream on MDIO, clocked by MDCLK. • Stream consists of management frames, each causing a PHY register to be read or written. • Registers 0 – 1: predefined, required • Registers 2 – 7: predefined, optional • Registers 8 – 15: reserved • Registers 16 – 31: vendor-specific 1-4

  5. Culture – Management Frame Format • Preamble – 32 consecutive 1’s • FS – start of frame • OP – read or write • PHY Address – 0 to 31; usually specified via PHY pins • Register Address – 0 to 31 • TA – Turnaround: separator between frame header and data • Data – 16 bits • Ends with high-impedance idle state 1-5

  6. MII PHY Predefined Registers • 0 – Control • 1 – Status • 2, 3 – PHY ID (manufacturer, model, rev; optional) • 4 – Auto Negotiation Advertisement (optional) • 5 – Auto Negotiation Link Partner (optional) • 6 – Auto Negotiation Expansion (optional) • 7 – Auto Negotiation Next Page Xmit (optional) Consult your PHY documentation for register usage 1-6

  7. Managing the PHY through MII From MII Address Register (0xFF800544) From MII Write Data Register (0xFF800548) Initiate by MII Command Register (0xFF800540) To MII Read Data Register (0xFF80054C) • Writes are initiated by writing to MWTD. • Read/write done when BUSY in MII Indicators Register (0xFF800550) returns to 0. 1-7

  8. Auto-Negotiation Exchange configuration information between two ends of a link segment and automatically select the highest common performance mode . When: • Power up • Reset (hardware and software) • Link failure and comes back up • Software re-start 1-8

  9. Parallel Detection • When partner does not support Auto-Negotiation • Automatically detect the presence of either link pulse (10 Mbps) or idle symbol (100 Mbps) and set speed accordingly. • Set Half mode. 1-9

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