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Implementation of DSP Algorithm on SoC

Implementation of DSP Algorithm on SoC. Mid-Semester Presentation. Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak The project is conducted with cooperation of Rafael. winter 2003/2004. Project Goals - Review.

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Implementation of DSP Algorithm on SoC

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  1. Implementation of DSP Algorithm on SoC

  2. Mid-Semester Presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak The project is conducted with cooperation of Rafael. winter 2003/2004

  3. Project Goals - Review • Studying and investigating the architecture of System on Programmable Chip (SoC). • Deciding on the Software/Hardware partition to be implemented. • Implementing a signal processing algorithm on the chosen platform. First Semester: • Full understanding of the elements and studied environments. • Running examples on the evaluation board.

  4. Project Schedule First Semester • Studying the VHDL programming language. • Get familiar with the FPGA structure. • Get familiar with the FPGA design process. • Studying Simulation and Synthesis programs. • Studying the Xilinx’s FPGA. • Studying Xilinx’s P&R program.

  5. 1. Studying the VHDL Programming Language. • Self-study from the Digital Lab’s CD and Guidance brochure of SITAL Technology. • ‘Rules of VHDL writing for synthesis’– two tutorials given by the digital lab. • Writing a FIFO example, Using a RAMB4_S1_S1 (4K*1 bit) component, of several implementations: • Building a 4K*8 bit memory space. • Buliding a 8K*1 bit memory space. • FIFO with Overflow. • Synchronized Fifo – using Empty/Full Flags.

  6. 2. Get Familiar with the FPGA Structure. Field Programmable Gate Array LUT Slice Logic Cell LUT FF FPGA CLB=8 LC = 4 Slices RAM CLB

  7. 3. Get Familiar with the FPGA Design Process. FPGA Design: • Requirements – the purpose and functionality of the device. • Architecture – Interfaces (In/Out signals) and a general block scheme. • Design – a specification of each block in the block scheme. • Implementation – writing the VHDL Code. • Simulations – both logical and using test vectors, to ensure rightness of previous stages. • Synthesis – building Gate-Level implementation. • Place & Route – building and downloading a bitstream for the final device. • Integration and debugging.

  8. Simulator Synth. P&R 3. Get Familiar with the FPGA Design Process (cont.) Flow: Editor .VHD .EDIF .BIT FPGA .EDN .EXO

  9. 4. Studying Simulation and Synthesis Programs. 4.1 Simulation program - ModelSim

  10. 4.2 Synthesis program Input: .VHD file with the code. Output: .EDIF file with the implementation of the design using the logic units of the chosen FPGA. Optimization of the design by adding constrains on signals and critical paths. Timing analysis. Provide a smooth transition to P&R. Leonardo 4. Studying Simulation and Synthesis Programs (cont.)

  11. 5. Studying the Xilinx’s FPGA “The Virtex II pro Family is a platform FPGA for designs that are based on IP cores and customized modules. The family incorporates multi-gigabit transceivers and PowerPC CPU cores. It empowers complete solutions for Telecommunications, Wireless, Networking, Video and DSP applications. Virtex II Pro devices are User-Programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs.”

  12. 5. Xilinx’s FPGA (cont) Components: • FPGA Logic: the RTL Design. • PowerPC MicroProcessor. • CoreConnect Bus – the Processor Local Bus (LPB). • Gigabit I/O. Functionality: • Serial Transceivers (serial->parallel; parallel ->serial). • PowerPC 405 RISC CPU (1 inst. Per cycle) • I/O • CLB (Comb. and Sync.) – 4 slices & 2 3-state buffers • RAM Memory • Clock Management circuitry (clock phase shifting, clock multiplication And division etc.)

  13. 6. Studying Xilinx’s P&R program Synthesis stages: compile Map P & R Implement • Placing the blocks • Wiring • Code analysis • Identification of logic structures • First optimization • Creating RTL View Creating the Physical Device • Implementation of structures • Optimization • Creating Technology View

  14. ISE–Integrated Software Environment Xilinx design software suite. Various options to start the design from (HDL, EDIF). Quick verification of the functionality of the sources using the integrated simulation capabilities (ModelSim). synthesis using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE (Leonardo). The Xilinx implementation tools continue the process into a placed and routed FPGA , and finally produce a bitstream for the device configuration. 6. Studying Xilinx’s P&R program (cont.)

  15. FPGA Block RAM FPGA Block RAM CoreConnect On-Chip Peripheral Bus (OPB) PowerPC 405 Core PLB-OPB Bridge Low Speed Peripherals D-Cache I-Cache CoreConnect Processor Local Bus (PLB) User Logic External Memory High Speed Peripherals System View

  16. Project ScheduleSecond Half of First Semester 10th week: Studying the PowerPC processor. 11th week: Studying the EDK software for developing SoC. 12th week: Studying the SoC design process. 13th week: Get familiar with the Xilinx’s evaluation board. 14th week: Writing and Running examples on the evaluation board.

  17. Thank You

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