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Flash Memory Built-In Self-Diagnosis with Test Mode Control. Jen-Chieh Yeh , Yan-Ting Lai, Yuan-Yuan Shih, and Cheng-Wen Wu. Laboratory for Reliable Computing (LaRC) Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan 30013. Outline. Introduction
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Flash Memory Built-In Self-Diagnosis with Test Mode Control Jen-Chieh Yeh, Yan-Ting Lai,Yuan-Yuan Shih, and Cheng-Wen Wu Laboratory for Reliable Computing (LaRC) Department of Electrical EngineeringNational Tsing Hua University Hsinchu, Taiwan 30013
Outline • Introduction • Flash Memory Diagnosis Methodology • BISD with Enhanced Test Mode Control • Experimental Results • Conclusions
Introduction • Flash memory is enjoying a rapid market growth • System integration and new applications drive the demand for flash technologies [ITRS 2003] • Embedded flash memory is gaining popularity in SOC applications • BIST and BISD are considered a good solution for flash memory testing and diagnosis
Flash Memory Fault Models • Flash memories are commonly tested for disturbance problems • Flash disturb fault models are defined in our DELTA02 and VTS02 papers • WPD, WED, BPD, BED, and OP faults are considered here for the BiNOR-type flash memory • SAF, TF, SOF, CFst and AF are also considered
BiNOR-Type Flash Memory • Bi-directional tunneling program/erase NOR-type flash memory • Low power consumption and excellent reliability Source: IEEE Trans. Electron Devices, 2001
Flash Memory Diagnosis Methodology SAF, TF, SOF, CFst, AF, Fault Models WPD, WED, BPD, BED, OP Fault Fault Dictionary (SA1) Simulator Error Catch Diagnosis March-FT and Analysis* Algorithm Parser (WPD) (to get Tester Log BISD signatures) (BPD) Fault Map Source: ICCAD00 Error Bit Map
Part of the March-FT Fault Dictionary • March-FT:{ (f); (r1,p0,r0); (r0); (f); (r1,p0,r0); (r0); }< 0 0 0 1 1 0 0 0 1 1 >
BISD with Enhanced Test Mode Control • Built-in March-FT algorithm • Programmable diagnosis algorithms • Flexible output format for test and/or diagnosis • Supports dynamic burn-in (BI) test • Engineering test mode can be accessed by BISD • Overall test time is reduced • Provides various types of access commands, e.g., Reset Wait
High Voltage (HI-V) Tests • HI-V tests usually employed to reduce the test time in the engineering test mode • TExecution(HI-V Erase) < TExecution(Erase) {A9, RSTB, OEB} HI-V Detector Normal flags Signal Memory {A[17:10], A[8:0]} Controller Test Collar DQ {WEB, CEB} Memory BISD Array
BISD Architecture 2 RBB BSI MUX CMD Reg. FSMofTPG WPB FOPC Look-Up Table 5 CLK CMDDecision FSMofCTR 8 I/O1 5 BRS ADDR Generator BMS MarchOp.Counter I/O Selector BNS 8 BIM I/O2 DB Generator& Comparator BAC BFI CEB WEB E-info. SelectorE-info. Register E-info.Collector Control Signal Generator 7 5 43 BSO REB CLE ALE BISD Controller(CTR) Test Pattern Generator(TPG)
Parallel Test Methods Original Program/Erase Unit Page buffer & SA Page buffer &SA Y-Decoder Block 0 Block 1024 Block 1 Block 1025 Block 2 Block 1026 Plane 0 Plane 1 FlashMemoryController Block 1023 Block 2047 Page buffer & SA Page buffer &SA Charge pump and other analog circuitry X-Decoder Proposed Program/Erase Unit
Experimental Results • BISD circuit implemented on FPGA • BISD test results compared with those of ATE
Results for 256Mb Flash Memory • Three chips are tested in this case • ATE test result: one passed and two failed • FPGA (BISD prototype) test results: two passed and one failed • The difference between ATE and FPGA is clock rate • Real BISD can perform at-speed test • Diagnosis result for the failed chip: one block cannot be erased (SA0) • Same for ATE & FPGA
Conclusions • We have proposed a flash memory diagnosis methodology and BISD design • Supports test, diagnosis, and BI modes • With enhanced test mode control • Area overhead is low • An FPGA-based low-cost flash memory diagnosis system is implemented • Real BISD required for at-speed test