Bio potential simulator

1. Bio potential simulator Instructor: EvgeniyKuksin Preformed by: ZivLandesberg Duration: 1 semester

2. Introduction Bio potential detector measures the electric potentials on the surface of living tissue . Bio potential detection is useful in many medical application such as ECG, EMG, AND EEG MONITORS. Therefore is also useful to have the ability to test the Bio potential detector by a bio potential simulator.

3. Project goal • The project goal is to implement a controller of a bio exponential simulator. The controller should control the signal at the output of the simulator.

4. System description • Material resembling • living tissue FPGA Host • BIO potential • Simulator

5. Project Block Diagram Sub-LSB Calibration System FPGA HOST Multi-Channel Voltage Generator 128ch@14bit 40KSps

6. In detailed block diagram Ultra Precision Vref 0.02% accuracy NI FPGA Calibration ADC 4ch@16bit Data/Control Data/Control DAC 32ch@14bit DAC 32ch@14bit DAC 32ch@14bit DAC 32ch@14bit Data/Control 128ch Data/Control Data/Control Sync 5v Return Current PS Isolation X4 * *For Analog crosstalk reduction

7. FPGA code structure • The code on the FPGA is divided to two main parts. • The first part is the calibration of the DACs m and c registers. This registers should allow to digitally set the slope to 1 and to eliminate the bias. (Did not supply with enough precision) • The second stage is the normal running of the system, which continuously read values from the DRAM and sending them to the D/As.

8. DACs timings at calibration Wait to host Reg,addres(always changed at same time) value value data Wr’ ldac

9. ADC timings at calibration Start new cycle at host command sdout write clock read write clock read din sck cnv

10. Dacs timings at normal runing Repeat 32 times Wait for output stabelize/wanted freq(optional) Wait to busy value value read Reg,addres(always changed at same time) data Wr’ ldac Read next 32 Values from dram

11. FPGA VI- hierarchy top Dac control Fill dram adc Single write Read 32 dram Rapid write Black-active during calibration Red-active during normal run Purple-active all the time

12. Fill DRAM • Fill the dram bank given by the host, always. • Each block in dram (64 bit) represents the values of single address on the 4 DAC’s. • The DAC address of a block is cyclic and can be calculated as DAC address=(dram_add-2)mod32 . • The Fill dram can fill a dram bank during the normal running , as long it is not being read at the same time!. • Each bank lasts for 16,777,184 /(32*40000)=13.106[sec]

13. Rapid-write • Loads all 128 DACs with a sample voltage. • Has 3 states: Wait, Pre-write, Write • “Wait” wait for begin of writing cycle/ until values from memory are read. • “Pre-write” set the values of the data to be written at DACs’ input(wr’ is down) • “Write” write the data(wr’ is up)

14. Read 32 dram • Read 32 blocks from the dram(128 values). Reads the values to be written at the next cycle of rapid write. • Has 2 main states : • 1- wait for beginning of new writing cycle. • 2- read next 32 blocks from given address and dram bank

15. Dac control • Control all the operation of the DACS in normal writing. Has 5 states: • “pre dram read”  pre dram read- waiting for end of calibration. Once ends the state never reappear • “busy/reading from dram”  wait for busy signal and until end of reading values from dram • “pre wrote ”  before writing, set the next dram address and the dram bank. • “writing”  writing to all DACS outputs • “ldac down-putting ”  down ldac begin update of analog output.

16. Graphs of timing at normal run Timing at dram bank switch

17. Zoom on graph from previous slide • 5.38 u sec per cycle

18. ADC • Control the adc- sends samples from wanted channel to host. Responsible for all of the ADC outputs. • Has 2 main states- • 1-reading serial data from the sdout output of the ADC. • 2- waiting until ADC ready to make another sample.

19. Single write • Write values to one output channel. The values and the channel are set directly by the host.

20. Calibration timing

21. Zoom on previous graph(5 u sec per cycle) Calibration ADC readout

22. Creation of Labview socketed clip • The creation of a socketed clip in labview is done by 2 simple stages . • The first one is to wire the I/O signals on the FPGA (agpio) according to the schematics of the project. • The second stage is to fill a XML file that declares names of the signals that can be used by labview.

23. The entity(base.vhd) of the VHDL part

24. Second part of entity

25. Xml file(myclip)

26. Image of clip in project

27. Calibration method • The calibration we chose use 4th order polynomial fit(software calibration), due to the fact that increasing the order did not improve the error we achieved(as will be shown in next slide). • The ADC uses external reference voltage with value of 5[volt] and accuracy of about 1[mV]. • After calibration DAC output error is less then 1mV FS is 5v  maximal error 0.02% (as accurate as ADC) • Before calibration DAC output error is around 10mV FS is 5v  error 0. 2% Accuracy Improvement x10

28. 4th order calibration-channel 0

29. 5th order calibration-channel 0

30. DAC0-channel 15

31. DAC0-channel 31

32. DAC1-channel 0

33. DAC1-channel 15

34. DAC1-channel 31

35. DAC2 channel 0

36. DAC3 –channel 31

37. Writing to dram while board is running • It is possible to write to the FPGA dram while it is writing values to the DAC. Is done by control active_dac2_host which says from which bank the fpgacurrentely taking is values(it is not possible to write to that bank) . • by the control dram_host, which says to which bank you want to write. • And by the fifofrom_host, simply by inserting the data you want to write.

38. Code for previous slide

39. Writing to dram while board is running

40. Activating 2 FPGA’s • At the last part of the project we inserted second FPGA (also connected to a board) and activated both of them at the same time through PXI backplane triggers. PXI NI FPGA NI FPGA PXI backplane With global triggers for nsecsynchronization

41. Step signal from 2 FPGA’swithout syncronization One DAC Sample

42. Signal with synchronization

43. System Expansion • By expanding and adding more FPGA and DAC boards we can easily get system with above 2000 Analog outputs.

44. Conclusion-summary • 128 channels analog outputs was successfully implemented. • PCB was manufactured and assembled in china. • PCB-PXI FPGA edge connector appeared 100% correct. Analog Outputs VHDC connector was designed correctly. • Calibration of all analog outputs was implemented and gave wanted 0.02% accuracy. • Slight PCB issues was found, corrected by local wire soldering. • Electrical Parameters Achieved: • 128 channels • All channels synchronized • 0-5v dynamic full scale range • Resolution – 14bit • Sample rate – 40KHz • Accuracy of 1mV (0.02%) • Synchronization of different boards is done by PXI triggers. • FW supports cyclic data transfer from Host to internal 512MB RAM. RAM bank switching allows unlimited data generation.

45. Test for data Generation • See VIDEO for ECG signals generation. • Data was taken from MIT ECG Arrhythmia Database. • Data is 20sec length. Data was divided into several chunks and was cyclically written to RAM banks.