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MIPS processor continued

MIPS processor continued. Jump Instruction. Jump instruction seems easy to implement We just need to replace the lower 28 bits of the PC with the lower 26 bits of the instruction shifted by 2 bits The shift is achieved by simply concatenating 00 to the jump offset. 31. 26. 25. 0. 0. 0.

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MIPS processor continued

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  1. MIPS processor continued

  2. Jump Instruction • Jump instruction seems easy to implement • We just need to replace the lower 28 bits of the PC with the lower 26 bits of the instruction shifted by 2 bits • The shift is achieved by simply concatenating 00 to the jump offset week-13-3.ppt

  3. 31 26 25 0 0 0 0 0 1 0 opcode Address Implementing Jumps • The one we have supports arithmetic/logic instructions, branch instructions, load and store instructions • We need also to support the jump instruction • What are the changes we need to make?

  4. Add j?

  5. Supporting Jump Instruction

  6. In Class Exercise – Supporting Jump Register week-14-1.ppt

  7. Performance • Assume that • Memory access: 200ps • ALU and adders: 100 ps • Register file read: 50ps • Register file write: 10ps (the clk-to-q delay) • PC update: 10ps (the clk-to-q delay) • The setup time of DFFs: 10ps • Other parts do not have delay • How fast is • An R-type instruction? • A lw instruction? • A sw instruction? • A beq instruction? • Need to find the critical path – the longest path

  8. R-type • So, the clock needs to be at least 10+200+50+100+10 = 370ps • Will there be a problem if the next instruction is also an R-type instruction, considering that the register is written and stable only after the next rising edge of the clock? • Figure not to the exact scale instruction ready register ready ALU ready register written PC ready

  9. lw • So, the clock needs to be at least 10+200+50+100+200+10 = 570ps • Figure not to the exact scale instruction ready Data mem ready register ready ALU ready register written PC ready

  10. beq • So, it is 10+200+50+100+10 = 370ps • Figure not to the exact scale instruction ready register ready ALU ready PC ready Adder 1 ready Adder 2 ready

  11. Clock cycle • So, how long should the clock cycle be? • Is it efficient?

  12. Control Signals • Control signals include ALUCtrl and the signals to control the 2-1 selectors • They are generated according to the current instruction, using the opcode [31-27] and the funct [5-0] field in the instruction.

  13. Datapath for Memory, R-type and Branch Instructions, plus the control signals

  14. The Effect of Control Signals

  15. Table for Control Line Setting Note: Branch is anded with ALU zero output to produce PCSrc

  16. Table for Control Line Setting

  17. Truth Table for Control Function

  18. Implementation Using PLA R lw sw beq The way to read this -- There are only 4 possible combination of inputs

  19. MIPS ALU unit

  20. ALU Control • Use Opcode to get ALUOp, then combine ALUOp with Funct • Two levels of decoding, more efficient • Assume ALUOp has been determined as such for each instruction week-13-3.ppt

  21. One Implementation ALU control bit 3 is always 0 for this set of instructions Can verify that the output is correct for lw, sw, beq For R-type, op2=F1, op1= ~F2, op0 = F3 | F0

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