EEL 3705 / 3705L Digital Logic Design

1. EEL 3705 / 3705LDigital Logic Design Fall 2006Instructor: Dr. Michael FrankModule #8: Introduction to Sequential Logic(Thanks to Dr. Perry for the slides)

2. Wednesday, October 25, 2006 • Administrivia: • This week’s lab: • Midterm practical exams • Homework assignment #4: • Due tonight • Midterm Exam #2: • Nov. 6 (a week from Monday) – Review on Nov. 1 • Plan for today’s lecture: • Start coverage of sequential logic

3. Introduction to Sequential Design

4. Types of Logic Circuits • Logic circuits can be: • Combinational Logic Circuits-outputs depend only on current inputs • Sequential Logic Circuits-outputs depends not only on current inputs but also on the past sequence of inputs

5. Sequential Circuit Models

6. Combinational Logic Delay Longest delay Shortest delay Longest timing delay = 5ns+5ns+5ns+5ns = 20ns Shortest timing delay = 5ns We will use the longest delay to represent the combinational logic (CL) delay, tcl

7. Combinational Logic (CL) Cloud Model Tcl=20ns Tcl=20ns

8. Memory

9. Memory • We will add memory (or registers) to our logic circuits. This will allow us to design sequential circuits.

10. Registers • We will represent registers with the following block diagram Clock and reset are control signals Ns and ps are data signals

11. Sequential Systems Block Diagrams

12. Sequential Systems General Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset CL= Combinational Logic Cloud Reg= D Registers

13. Sequential SystemsGeneral Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset X is the input data vector Y is the output data vector

14. Sequential SystemsBlock Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset Ns is the next state data vector Ps is the present state data vector

15. Sequential SystemsBlock Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset Notice we have a feedback path which combines the ps data vector with the input vector to generate a new ns data vector.

16. Sequential SystemsBlock Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset Mathematically, we say Or, ns is a function F of X and ps and Y is a function H of ps.

17. F Logic Register Example Circuit Schematic ns ps X input H Logic (buffer) Block Diagram

18. F Logic Register Example Circuit Schematic ns ps X input H Logic (buffer) State Equations

19. Finite State Machine (FSM) General Models

20. Moore FSM General Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset CL= Combinational Logic Cloud Reg= D Registers

21. Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

22. Mealy FSM Block Diagram and State Equations Next State Present State Input Vector Output Vector Feedback Path Output Y is also a function of input X

23. Mealy-Moore FSM Block Diagram and State Equations Present State Next State Input Vector Mealy Outputs Moore Outputs

24. State Diagrams

25. State Bubble

26. State Bubble Example Conditional Transition Unconditional Transition State name = S0 State value = 00 Y = 0 for this state We leave this state if upn=1, We remain in this state if upn=0

27. Memory Devices

28. Memory Devices • Data Latch (D-latch) • Flip-flops (edge triggered) • D-FF, D Register • JK-FF • T-FF

29. D-FF Positive Edge TriggeredBlock Diagram Symbol 4 inputs: D,Clk,Pre,Rst One output: Q D = Data Input Clk = Clock Input Pre = Preset Input Rst = Reset Input

30. D-FF Truth Table Symbol Truth Table Equation (rising clock)

31. D-FF Truth Table Symbol Truth Table Equation (rising clock) Pre= Preset Input (active low) Rst = Reset Input (active low) Highest priority

32. D-FF Truth Table Symbol Truth Table Equation (rising clock) D = Data Input Clk = Clock input Qn = Register Output

33. FSM Examples

34. Example– 2-bit Up Counter • State Diagram Clock is implied

35. Example – 2-bit Up Counter • State Table State Value Assignment Let Output Vector Let S0 = reset state

36. Example – 2-bit Up Counter • Truth Table

37. Example – 2-bit Up Counter • Excitation Equations

38. Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

39. Reg Block F Logic Y Vector H Logic Logic Diagram No X Vector in this Example No H Logic needed

40. Logic Diagram

41. Flash Animation

42. Example 3– 2-bit Down Counter • State Diagram Clock is implied

43. Example – 2-bit Down Counter • State Table Let Let S0 = reset state

44. Example – 2-bit Down Counter • Truth Table

45. Example – 2-bit Down Counter • Excitation Equations

46. Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

47. Logic Diagram Reg Block F Logic Y Vector H Logic No X Vector in this Example

48. Logic Diagram

49. Example 4 – 2-bit Up/Down Counter • State Diagram

50. Example – 2-bit Up/Down Counter • State Diagram Shorthand Notation