MKE1503/MEE10203 Programmable Electronics

1. MKE1503/MEE10203Programmable Electronics CPLD and FPGA Architectures Computer Engineering Department Faculty of Electrical and Electronic UniversitiTun Hussein Onn Malaysia

2. Definitions • Field Programmable Device (FPD): • a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured “in-system”. Another name for FPDs is programmable logic devices (PLDs). Source: S. Brown and J. Rose, FPGA and CPLD Architectures: A Tutorial, IEEE Design and Test of Computer, 1996

3. PLDs • 16V8 (20 Pins) • can have 16 inputs (max) and/or 8 outputs (marcrocells) • has 32 inputs to each of the AND gates (product terms) • 22V10 (24 pins) • can have 22 inputs and/or 10 outputs (max) • has 44 inputs to each of the AND gates • How about a “128V64” for larger applications? • It will be slower and will more wasted silicon space • Solution? Use CPLDs Lect #14 Rissacher EE365

4. The OR gates XOR gates to make inverting or non-inverting buffer GAL16V8(review seq_1.ppt) • Each output is programmable as combinational or registered • Also has programmable output polarity And Plane Lect #14 Rissacher EE365

5. Classifications of Early Programmable Logic • PLA — a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND- plane and an OR-plane, where both levels are programmable • PAL— a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane • SPLD— refers to any type of Simple PLD, usually either a PLA or PAL • CPLD— a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. • FPGA— a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity.

6. Programmable AND Plane Programmable OR Plane Programmable Node Un-programmed Connect Disconnect X O1 O2 O3 O4 Y XY X XY Y XY XY X X Y Y PLA

7. Programmable AND Plane Programmable OR Plane YZ XZ XYZ XY ? ? X Y XY+YZ Z XZ+XYZ PLA

8. PAL Programmable AND Plane Fix OR Plane X O1 O2 O3 O4 Y

9. PAL with Logic Expanders Programmable AND Plane Fix OR Plane ? Logic expanders

10. PLA v.s. PAL • PLAs are more flexible than PALs since both AND & OR planes are programmable in PLAs. • Because both AND & OR planes are programmable, PLAs are expensive to fabricate and have large propagation delay. • By using fix OR gates, PALs are cheaper and faster than PLAs. • Logic expanders increase the flexibilities of PALs, but result in significant propagation delay. • PALs usually contain D flip-flops connected to the outputs of OR gates to implement sequential circuits. • PLAs and PALs are usually referred to as SPLD.

11. PAL-like block PAL-like block I/O block I/O block Programmable interconnect PAL-like block PAL-like block I/O block I/O block CPLD • A CPLD comprises multiple PAL-like blocks on a single chip with programmable interconnect to connect the blocks. • CPLD Architecture

12. A General CPLD structure A collection of PLDs on a single chip with Programmble interconnects Lect #14 Rissacher EE365

13. Let’s takes a look at this Who makes the CPLDs? Manufacturer CPLD Products URL AlteraMAX 5000, 7000 & 9000 www.altera.com Altmel ATF & ATV www.atmel.com Cypress FLASH370, Ultra37000 www.cypress.com Lattice ispLSI 1000 to 8000 www.latticesemi.com Philips XPLA www.philips.com Vantis MACH 1 to 5 www.vantis.com Xilinx XC9500 www.xilinx.com Lect #14 Rissacher EE365

14. Altera MAX CPLD I/O Cell LAB (Logic Array Block) LAB LAB LA (local array) • • • LAB LAB LAB LAB Altera MAX chip Macroccell Chip-wide interconnect • Each LAB contains 16 macrocells

15. Macrocell of Altera MAX CPLD System clock System enable Local Array Clock, clear, preset, enable 3 Programmable inversion OUT M D Q 5 Product term select Parallel expander To next macrocell 114 Macrocell MAX 9000 has 33 inputs, can you explain why LA has 114 inputs?

16. FPGAs • Historically, FPGA architectures and companies began around the same time as CPLDs • FPGAs are closer to “programmable ASICs” -- large emphasis on interconnection routing • Timing is difficult to predict -- multiple hops vs. the fixed delay of a CPLD’s switch matrix. • But more “scalable” to large sizes. • FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD. Lect #14 Rissacher EE365

17. FPGA • FPGA consists of an array of programmable basic logic cells surrounded by programmable interconnect. • FPGA Structure Programmable interconnect Logic cell I/O Cell

18. FPGA v.s. CPLD • Capacitance • Applications CPLDs FPGAs • Implement random glue logics or Replace circuits previously implemented by multiple SPLDs • Circuits that can exploit wide AND/OR gates, and do not need a very large number of flip-flops are good candidates for implementation in CPLDs. • FPGAs can be used in various applications: prototyping, FPGA-based computers, on-site hardware re-configuration, DSP, logic emulation, network components, etc.

19. Problems common to CPLDs and FPGAs • Pin locking • Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pinout. • Locking too early may make the resulting circuit slower or not fit at all. • Running out of resources • Design may “blow up” if it doesn’t all fit on a single device. • On-chip interconnect resources are much richer than off-chip; e.g., barrel-shifter example. • Larger devices are exponentially more expensive. Lect #14 Rissacher EE365