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Research supported by CAPES and CNPq Brazilian Agencies

Designing a Radiation Hardened 8051-like Micro-controller. Fernanda G. de Lima Érika Cota Luigi Carro Marcelo Lubaszewski Ricardo Reis. Sana Rezgui Raoul Velazco. Institut National Polytechnique de Grenoble TIMA Laboratory Grenoble, France. Universidade Federal do Rio Grande do Sul

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Research supported by CAPES and CNPq Brazilian Agencies

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  1. Designing a Radiation Hardened 8051-like Micro-controller Fernanda G. de Lima Érika Cota Luigi Carro Marcelo Lubaszewski Ricardo Reis Sana Rezgui Raoul Velazco Institut National Polytechnique de Grenoble TIMA Laboratory Grenoble, France Universidade Federal do Rio Grande do Sul Instituto de Informática Porto Alegre, Brasil Research supported by CAPES and CNPq Brazilian Agencies

  2. Outline 1 Motivation 2 Radiation Effects 3 Objective: Hardening a processor by EDAC 4 SEU-hardened 8051 like micro-controller 5 Prototyping the robust 8051 using THESIC platform 6 Area overhead results 7 Conclusions

  3. 1 Motivation Why do we need to protect electronic circuits? • Military, avionics and aerospace applications • run under radiation where the electronic systems are sensitive to upsets • utilize advanced electronic systems based on microprocessors • Electronic systems • operating in low levels of the Earth atmosphere are becoming more sensitive to radiation due to the progressive transistor size shrink.

  4. Circuit level: • Epi-bulk CMOS process • SOI CMOS process Permanent Faults Total Ionization Dose (T.I.D.) • Circuit level: • SOI CMOS process • Design level: • Hardened memory cells • EDAC (Hamming Code, • Reed-Solomon, ...) • Triple Modular Redundancy • System level: • Self-checkers Single Event Upsets (S.E.U.) Transient Faults Single Event Effects (S.E.E.) • Circuit level: • Epi-bulk CMOS process • SOI CMOS process Single Event Latchup (S.E.L.) 2 Radiation Effects Some Mitigation Techniques

  5. 3 Hardening a Microprocessor by EDAC • Goal: • To protect a microprocessor to Single Event Upset. • Methodology: • To insert fault tolerant structures based on the Hamming Code technique in the microprocessor VHDL description. • The Hamming Code protection was inserted in all the microprocessor SEU sensitive area.

  6. 3 Microprocessor 8051 • The Hamming code structures were implemented in a 8051 original VHDL description [CARRO, RSPW’96] • This 8051 like micro-controller is: • entirely compatible with the INTEL 80c51 • contains 44 instructions that are executed in 12 or 24 clock periods • divided into 6 main blocks: control unit, datapath unit, state machine, instruction unit, ROM and internal RAM

  7. 4 SEU-Hardened 8051 • Why 8051 micro-controller? • widely used in space applications • large amount of data about its behavior under radiation • protection of all systems that are already running based on the 8051 • Why do we use Hamming Code? • High reliability circuits: detect and correct errors • 100% of efficiency for data single event upset • Possible implementation in VHDL for fast prototyping • Disadvantage: Area overhead: check bits, code and decode logic blocks

  8. 3 SEU Sensitive area in 8051 1 CLOCK RESET STATE (4-0) Control + State machine INSTRUCTION (7-0) Instruction unit INT0 5 P1.7 acc_status PSEN INC_PC 2 4 LD_IR IR (7-0) ... 6 PC_PORT CLOCK Datapath ACC_PORT RESET DATA (7-0) 3 ROM ADDRESS (15-0) Internal RAM memory

  9. 3 Upset effects in the sensitive area • Software fault injection experiments in the Intel 8051 microprocessor [VELAZCO, NSREC’00] shows: Total random Injected errors 49,96% 47,24% 2,8%

  10. Hamming Code Protection • The Hamming code satisfies the relation 2m >= n +1, • n is the total number of bits in the data • m is the number of check bits in the data • EDAC technique: • Error-detecting (all single and double-bit errors) • Error-correcting (all single-bit errors) data Check bits (Detect the position of the error) m = 5 n = 16

  11. 8-bit data Hamming Codification, check bits generator 12-bit data Hamming Decodification, 1-bit error correction Hamming Code Protection • For an 8-bit data (n=8), it is necessary 4 check bits in the data (m=4), 24 >= 8+1 • It is necessary a logic to codify and decodify each n-bit data • The size of each Hamming code/decode blocks grows proportional to the increase of the protected data bits.

  12. 4 Designing the SEU-Hardened 8051 • Four structures in the 8051 VHDL description have been protected by Hamming Code: a) Control Unit b) Finite State Machine c) RAM Memory d) Registers in Datapath. • The Instruction unit is a completely combinational structure and in principle it is not subject to bit flips, making no protection schemes for it.

  13. code Protected register decode 4a SEU-Hardened Control Unit It represents 1.2% of the 8051 sensitive area. • 72% more memory cells • 6 group of logic code and decode (more combinational area) Latch_int0 interrupt_state instruction Hamming Code Latch_int0 interrupt_state instruction

  14. 4b SEU-Hardened State Machine It represents 1.3% of the 8051 sensitive area • 80% more memory cells • 6 group of logic code and decode (more combinational area) state next_state current_state code Hamming Code Protected register state next_state current_state decode

  15. Hamming Code ... ... RAM RAM 4c SEU-Hardened Internal Memory It represents 88% of the 8051 sensitive area code • 50% more memory cells • 2 group of logic code and decode (more combinational area) data decode RAM address

  16. code decode 4d SEU-Hardened Datapath (I) It represents 9.5% of the 8051 sensitive area ALU input a ALU input b ALU output PC PC_2 SP ACCU Instruction Inbus RAM output RAM address low RAM address high ROM output Hamming Code ... • 50% more memory cells • 26 group of logic code and decode (more combinational area)

  17. ROM data PC decode decode 12-bit data Datapath add/sub PC code RAM memory AD_low decode AD_high All the registers are 12-bit (coded by Hamming Code) decode decode decode data code ROM memory decode code AD ALU 4d SEU-Hardened Datapath (II) Full protected datapath using less logic blocks for coding and decoding:

  18. 5 THESIC platform THESIC (Testbed for Harsh Environment Studies on Integrated Circuits) [VELAZCO, ETW98] is a platform for SEU ground testing purposes. Thesic Mother board Thesic Daughter board

  19. 5 8051 Prototype Daughter Board DUT MMI ROM Datapath Instruction unit External memory Control + State Machine Internal memory Mother Board of THESIC Connection to PC

  20. pins cells EPM9560 208 560 EPM9400 84 400 5 8051 Prototype Daughter Board (cont.) • The board uses 3 PLDs from Altera MAX9000 family • The size of the PLD EMP9560 was a limitation for the full SEU-hardened Datapath implementation • Some not full SEU-hardened Datapath versions were developed aiming to fitting in the EPM9560 device • 8051 on the board runs at 4 MHz (1) (2)

  21. version Control State Machine RAM Datapath 8051 A 8051 B 8051 C 8051 D 8051 E 8051 F 8051 G 8051 H 8-bit PC PC, ACCU 16-bit PC PC, ACCU Hamming Code protection 5 Versions of the robust 8051 • There are 8 developed versions of the 8051:

  22. 6 Fault injection results in memory • The internal memory protected by Hamming Code shows the smallest area overhead • Performed software fault injection experiments in the Intel 8051 with a supposed protected internal memory [COTA, LATW00] shows: Total random Injected errors 97.94 % 69.7 % 1.33 % 19.6 % 0.73 % 10.7 %

  23. # code / decode blocks Sensitive Area overhead (%) SEU-Hardened #CLBs 72 80 50 50 50 Control Unit State Machine Internal Memory Datapath (I) Datapath (II) 06 06 02 26 10 36 42 44 186 70 data length (n) Percentage of sensitive area overhead Code/decode logic blocks size 6 Overhead Area Results

  24. State Machine version #flip-flops* #CLBs Control RAM Datapath 8051 A 8051 B 8051 C 8051 D 8051 E 8051 F 8051 G 8051 H 130 150 158 202 138 158 170 214 536 692 824 909 579 728 909 987 8-bit PC 55% 69% PC, accu 55% 16-bit PC 70% PC, accu Hamming Code protection * flip-flops implemented inside the PLD 6 PLD implementation Results

  25. 7 Radiation Ground Test • Radiation Testing is scheduled October 2000 at I.N.P. (Orsay, France) • Particle accelerator TANDEM Van de Graaff • Heavy Ions Test Application: Multiplication of two matrixes 6x6 • Experimental results will allow us to evaluate the trade-off between the area overhead and the protected sensitive area

  26. 7 Conclusion and Future Work • Different versions of a SEU hardened 8051-like micro-controller protected by Hamming Code were presented. • All the internal registers and memory were protected by the Hamming code. • Experimental results proving Hamming Code efficiency in the micro-controller 8051 should be evaluated in the radiation ground test. • Space Application systems using the 8051 micro-controller can be SEU-hardened using this version of the 8051.

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