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Lecture #28 PMOS

Lecture #28 PMOS. LAST TIME: NMOS Electrical Model NMOS physical structure: W and L and d ox , TODAY: PMOS Physical structure CMOS Dynamic circuits (Ring oscillators). In this device the gate controls electron flow from source to drain.

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Lecture #28 PMOS

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  1. Lecture #28 PMOS • LAST TIME: NMOS Electrical Model • NMOS physical structure: W and L and dox, • TODAY: PMOS • Physical structure • CMOS • Dynamic circuits (Ring oscillators) EE 42 fall 2004 lecture 28

  2. In this device the gate controls electron flow from source to drain. (in the absence of gate voltage, current is blocked) n n n n N-MOS source drain VGS > Vt P - + gate oxide insulator oxide insulator drain source P NMOS =device which carrier current using electrons but on the surface of a p-type substrate (p-type substrate means that no electrons are available) gate If we increase gate voltage to a value greater than Vt then a conducting channel forms between source and drain. (“Closed switch”) EE 42 fall 2004 lecture 28

  3. In this device the gate controls electron flow from source to drain. n n N-MOS source drain P gate oxide insulator P-MOS drain source In this device the gate controls hole flow from source to drain. p p n-type Si CMOS = Complementary MOS(PMOS is a second Flavor) gate It is made in p-type silicon. The NEW FLAVOR!P-MOS It is made in n-type silicon. (In n-type silicon no positive charges (“holes”) are normally around.) EE 42 fall 2004 lecture 28

  4. gate P-MOS drain source n-type Si |VGS |>|Vt | + - gate drain In this device the gate controls hole flow from source to drain. p p p p n-type Si source PMOS It is made in n-type silicon. What if we apply a big negative voltage on the gate? If |VGS |>|Vt | (both negative) then we induce a + charge on the surface (holes) EE 42 fall 2004 lecture 28

  5. ID ID VGS=3V VGS= 3V 1 mA 1 mA (for IDS = 1mA) (for IDS = -1mA) VGS=0 VGS=0 VDS VDS 2 4 1 3 2 4 1 3 NMOS and PMOS Compared NMOS “Body” – p-type Source – n-type Drain – n-type VGS – positive VT – positive VDS – positive ID – positive (into drain) PMOS “Body” – n-type Source – p-type Drain – p-type VGS – negative VT – negative VDS – negative ID – negative (into drain) G G S S D D ID ID n p n p n B B EE 42 fall 2004 lecture 28

  6. PMOS circuit symbol D D G G S S CIRCUIT SYMBOLS NMOS circuit symbol A small circle is drawn at the gate to remind us that the polarities are reversed for PMOS. EE 42 fall 2004 lecture 28

  7. VDD VDD S S S VG =0 G G G VDD VG = VDD V=0 D D D Switch OPEN Switch CLOSED Switch is closed: Drain (D) is connected to Source (S) when VG =0 Switch is open : Drain (D) is disconnected from Source (S) when VG = VDD PMOS Transistor Switch Model Operation compared to NMOS: It is complementary. For PMOS for the normal circuit connection is to connect S to VDD (The function of the device is a “pull up”) EE 42 fall 2004 lecture 28

  8. S CGS G S G RDP D D The Switch model PMOS Model Refinement PMOS transistor has an equivalent resistance RDPwhen closed There is also a gate capacitance CGS, just as in NMOS P Ch The circuit symbol EE 42 fall 2004 lecture 28

  9. CMOS Challenge: build both NMOS and PMOS on a single silicon chip NMOS needs a p-type substrate PMOS needs an n-type substrate Requires extra process steps D G G D S S oxide P-Si n-well p p n n EE 42 fall 2004 lecture 28

  10. VDD source Vin Vout V DD drain PMOS drain v v in out source VDD NMOS Vin Vout THE BASIC STATIC CMOS INVERTER For Vin> 1.5V NMOS on , PMOS off Vout = 0 For Vin< 1VNMOS off , PMOS on Example for Discussion: NMOS: VTn = 1 V PMOS: VTp = -1 V Let VDD = 2.5V Vout = VDD EE 42 fall 2004 lecture 28

  11. VDD source Vin Vout V DD drain PMOS drain v v in out source VDD NMOS Vin Vout THE BASIC STATIC CMOS INVERTER Quasi-static operation (ignoring transients) For Vin> 2V NMOS on , PMOS off Vout = 0 For Vin< 0.5VNMOS off , PMOS on Example for Discussion: NMOS: VTn = 0.5 V PMOS: VTp = - 0.5 V Let VDD = 2.5V Vout = VDD EE 42 fall 2004 lecture 28

  12. V DD PMOS v v in out NMOS CMOS INVERTER TRANSFER CURVE EE 42 fall 2004 lecture 28

  13. V V V V DD DD DD DD VDD VDD v in STAGE M Vin Vout CHAIN OF CMOS INVERTERS Vout If the input is toggled, the state of every inverter will change and there will be a gate delay for every gate caused by the combination of the output resistance of the switching devices combined with the input capacitance of the following stage. Let’s estimate the stage delay. EE 42 fall 2004 lecture 28

  14. “Open” the model V V DD DD VDD CGP VM VM VM+1 VM+1 RN CGN M M+1 “Closed” CHAIN OF CMOS INVERTERS STAGE-M gate delay if input HIGH VDD When the input VM is high, the lower (NMOS) switch is closed and according to our model the resistor RN discharges the input capacitance of the next gate, the capacitors CGN and CGP in parallel. The time constant is RN(CGN+CGP) so the gate delay is 0.69 RN(CGN+CGP) . We do not consider here the capacitance of the gates in Stage M, because they load Stage M-1, and contribute to its delay. EE 42 fall 2004 lecture 28

  15. V = VDD 2 Capacitors share one node; the other nodes are held at constant voltages. C i ( t ) 2 2 i ( t ) v ( t ) C i ( t ) C 1 KCL: currents sum at common node, ie node capacitance is SUM (parallel capacitor formula). 1 V = 0 1 Core Circuit for “Pull-Down” Transition Circuit only contains one resistor and two capacitors Capacitors CGp and CGn … how can they be combined into one? “Virtually Parallel” Capacitors EE 42 fall 2004 lecture 28

  16. t = 0+ v out1 Precharge: VDD D V C + C DD Gn Gp R n v = out1 v in2 v out2 + v in1 - Pull-Down Equivalent Circuit Two capacitors add for finding the charging current  applies to gate capacitances Lets once more associate circuit above to the actual inverter circuit. EE 42 fall 2004 lecture 28

  17. t = 0+ v out1 Precharge: VDD D C + C Gn Gp R n V DD v out1 v in2 v out2 + v in1 - Equivalent circuit vs actual circuit 1) Remove inactive device 2) Replace load devices by their input equivalents 3) Replace NMOS pull-down by by its output equivalent. EE 42 fall 2004 lecture 28

  18. t = 0+ v out1 Precharge: VDD D C + C Gn Gp R n Vout1 VDD VDD exp(-t/RC) VDD 2 0.69 t/RC Gate Delay from Pull-Down Equivalent Circuit Capacitor is precharged to VDD and discharged to ground through resistance Rn. We can compute the delay easily. It is just an RC delay. If we define the switching delay as the time for the output voltage to swing halfway to its new steady-state value, we will find the switching delay is 0.69RC. [remember 0.5 = exp(-0.69)] EE 42 fall 2004 lecture 28

  19. the model “CLOSED” VDD V V DD DD VDD RP CGP VM VM VM+1 VM+1 CGN M M+1 “Open” CHAIN OF CMOS INVERTERS STAGE-M gate delay if input LOW When the input VM is low, the upper (PMOS) switch is closed and according to our model the resistor RP charges the input capacitance of the next gate, the capacitors CGN and CGP in parallel. The time constant is RP(CGN+CGP) so the gate delay is 0.69 RP(CGN+CGP). Normally we try to have equal rising and falling gate delay, so for the simple inverter we design the transistors so RP = RN. EE 42 fall 2004 lecture 28

  20. CMOS PARAMETERS 3 generations of CMOS Return EE 42 fall 2004 lecture 28

  21. Interconnect layers • On top of the transistor layers, many metal layers interconnect the logic Illustration Actual TEM photo EE 42 fall 2004 lecture 28

  22. STAGE 101 STAGE 1 VDD Vout CHAIN OF CMOS INVERTERS TO MEASURE tdelay If the input is toggled, the state of every inverter will change and there will be a gate delay for every gate. Suppose there are 1001 gates and we move the input switch from VDD to ground. 1001 gate delays later the output will go from ground to VDD. But suppose in the meantime we moved the switch to connect to Vout (which is initially zero). At at time equal to exactly 1001 gate delays, the input to stage 1 will go high, and after another equal time it will go low, etc. We have created a “RING OSCILLATOR”, which toggles at a frequency equal to 1/(1001 tdelay ). Such ring oscillators are commonly used to estimate the performance of a technology. No switch is actually needed, the output is permanently wired to the input, and the oscillations start when power is applied. EE 42 fall 2004 lecture 28

  23. VDD Vout CLOAD VDD D R p Vout R n CLOAD CMOS INVERTERS DRIVING ANY LOAD No matter what the load is, the behavior is the same: the stage delay is 0.69RC where C= CLOAD and R= RN if input is switched high or R= RP if input is switched low. If we substitute the switch model for the transistors we have the following circuit: The actual load consists of whatever gates are attached to the node plus any additional capacitance. In the next lecture we will compute the gate capacitance on the input to any NAND logic block for example. As another example, if an external wire is attached to a node with the wire going to a printed circuit board, we will have a load of several pF. EE 42 fall 2004 lecture 28

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