Assembling 2D Blocks into 3D Chips

1. Assembling 2D Blocks into 3D Chips Johann Knechtel, Igor L. Markov and Jens Lienig University of Michigan, EECS Department, Ann Arbor USA Dresden University of Technology, EE Department, Dresden Germany ISPD’11

2. Outline • Introduction • Background • Problem Formulation • Method • Experimental Result

3. Introduction • 3D IC. • Stacking multiple dies and implementing vertical interconnections with Through-Silicon Vias (TSVs). • Focus on design styles that reuse existing 2D Intellectual Property (IP) blocks. • Modern chip designs are dominated by 2D IP blocks, proven in applications and considered reliable.

4. Introduction • Design Style • R2D L2D Gate-level and Redesigned 2D (R2D) styles place TSVs (small boxes) within the block footprint. Legacy 2D (L2D) style places scattered TSVs between blocks

5. Background • L2Di L2D style with TSV islands (L2Di) groups TSV to blocks.

6. Background • Why TSV island? • Stress • TSVs introduce stress in surrounding silicon which affects nearby transistors. • TSV redundancy architectures TSV islands can incorporate spare TSVs for redundancy.

7. Background • Wirelength estimation • Neti = { P1, P2} with TSVia ( red block)

8. Problem Formulation • Inputs • Active layers • Rectangular IP blocks • Netlist • TSV-island types • 3D floorplanby[32] • 3D integration with the L2Di style seeks to cluster inter-layer nets into TSV islands, and to insert TSV islands into aligned deadspace around floorplan blocks. • If TSV-island insertion is impossible due to lack of aligned deadspace, blocks can be shifted from their initial locations, but their relative positions must be preserved.

9. Method

10. Method Control the clustering algorithm Control the deadspace search for TSV island insertion Control the global iteration Parameters for net clustering and TSV-island insertion algorithms

11. Net Clustering • Phase 1 • Construct Virtual die and grid structure • Phase 2 • Determine possible clusters • Phase 3 • Determine deadspace for clusters

12. Net Clustering • Phase 1 • Construct Virtual die and grid structure N1 = {p1 , p5} N2= {p2 , p4} N3= {p3 , p5}

13. Net Clustering • Phase 2 • Determine possible clusters

14. Net Clustering • Phase 3 • Determine deadspace for clusters

15. Insert TSV Island • Phase 4 • Sort nets • Phase 5 • Assign nets to clusters • Phase 6 • Mark & unlink handled nets from clusters

16. Insert TSV Island • Phase 4 • Sorts all nets by their total aligned deadspace of related clusters.

17. Insert TSV Island • Phase 5 • Assign nets to highest-scored cluster

18. Insert TSV Island • Phase 6 • Mark & unlink handled nets from clusters

19. Experimental Results Parameters for net clustering and TSV-island insertion algorithms, along with their values.

20. Experimental Results HPWL ratio divides wirelengthof connections through TSVs by shortest-path wirelengths.

21. Experimental Results

22. Conslusions • A key insight in our work is that many of the benefits of 3D integration can be obtained while reusing existing 2D blocks. • In the near future, the most promising and least risky design style for 3D integration is the L2Di style. • To enable the L2Di style, we contribute novel techniques for clustering of nets and inserting TSV islands.