1 / 30

COMS 361 Computer Organization

COMS 361 Computer Organization. Title: Memory and Multiplication Date: 11/09/2004 Lecture Number: 18. Announcements. Review. Logic design Decoder Multiplexor PLA Simple ALU. Outline. Memory elements SR flip-flop (unclocked) D Latch (clocked) D flip-flop (clocked)

lyle
Download Presentation

COMS 361 Computer Organization

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. COMS 361Computer Organization Title: Memory and Multiplication Date: 11/09/2004 Lecture Number: 18

  2. Announcements

  3. Review • Logic design • Decoder • Multiplexor • PLA • Simple ALU

  4. Outline • Memory elements • SR flip-flop (unclocked) • D Latch (clocked) • D flip-flop (clocked) • Master-Slave flop-flops • Clock • Multiplication • Floating point numbers

  5. Memory Elements • Store a state • Latches (level triggered) • Flip-flops (edge triggered) • Register files • Latches • Output is the value of the stored state • Simplest • Unclocked • SR latch (set-reset)

  6. SR Latch • R = S = 0 • The output Q is its previous value • NOR gates act as inverters (homework) • If Q is asserted (1) • Bottom inverter output is unasserted (0) • Input to the top inverter • Q remains asserted (1)

  7. SR Latch • R = 0, S = 1 • Q = 1 • Input to the top inverter (R) is 0 • Output Q = 1 • Input to bottom inverter is 1 • Output Q’ = 0 • Both inputs to the top inverter are 0, Q = 1

  8. SR latch • R = 1, S = 0 • Q = 0 • Input to the top inverter (R) is 1 • Output Q = 0 • Input to bottom inverter is 0 • Output Q’ = 1 • Both inputs to the top inverter are 1, Q = 0

  9. SR latch • R = S = 1 • Unstable

  10. Memory Elements • Clocked • Additional input (clock) • State changes are triggered by the clock • Flip-flop • Changes state on the leading or falling clock edge • Clocked Latch • Changes state when • Inputs change appropriately • Clock is 1 • We will use flip-flops (an edge triggered scheme) • Built from latches

  11. Memory Elements • D latch • Simple memory element • Stores the value of its input • Two inputs • Data value to be stored (D) • Clock (C) • Indicates when the data value (D) is read and stored • Two outputs • Stored value • Stored value complement

  12. Falling edge Rising edge clock period Clock high Clock low Clock asserted Logic 1 Logic 0 unasserted

  13. D latch • C = 1 • Latch is open • Output (Q) becomes the value on input D • C = 0 • Latch is closed • Output is the stored value

  14. D latch • Timing diagram • Shows temporal relationship among elements • Q takes on the value of D when C is asserted (1) • Said to be a transparent latch • Q holds its value when C is not asserted (0)

  15. D flip-flop • State changes only on the clock edge • Can be the rising or falling edge • Built from two D latches • Master and slave

  16. D flip-flop • When C is asserted • Master is open • Follows the D input • When C is unasserted • Master is closed • Slave is open • Stores the output from the master

  17. D flip-flop

  18. D Q D Q C D flip-flop • Circuit diagrams do not show the flip-flop details

  19. Memory elements • Set-up time • Time data must be stable before the clock comes • Hold time • Time data must be stable after the clock comes

  20. Multiplication • Multiplication Hardware • Implements simple algorithm

  21. Multiplication • More complicated than addition • Accomplished via shifting and addition • 3 versions based on grade school algorithm 0010 (multiplicand)x 1011 (multiplier) 0010 (intermediate product) 00100(intermediate product) 000000(intermediate product) 0010000(intermediate product) 0010110(sum of intermediate products)

  22. Multiplication (version 1) • Product size • Multiplicand size + multiplier size • MIPS product 64 bits • Accumulate product term by term • Terms • Intermediate products • Left shifted multiplicand • All zeros • Determined by the bit pattern of the multiplier

  23. Multiplication (version 1)

  24. Multiplication (version 1) • Left shifted multiplicand • Multiplicand register size must be at least • Multiplicand bits + multiplier bits long • ALU size same as the multiplicand register

  25. 0001 0000 x 0001 0000 0100 x 0101 0001 0110 0000 1000 x 0010 Multiplication (version 1) 0000 0010 x 1011 0000 0010 0001 0000 + 0000 0110 0001 0110 0000 0100 + 0000 0010 0000 0110 0000 0000 + 0000 0110 0000 0110

  26. Multiplication (version 2) • At least half the multiplicand bits are zero • Waste to make a 64 bit adder • Left shift inserts zeros on the right end of multiplicand • Right part of the product will not change • Shift the product register right instead • Fixes the multiplicand • 32 bits • Multiplicand register • ALU

  27. Multiplication (version 2)

  28. x 0001 x 0101 0010 1100 0001 0110 Multiplication (version 2) 0010 0010 x 0010 x 1011 0000 0000 0010 0000 0001 1000 + 0000 0000 0001 1000 0010 0000 0000 1100 0001 0000 0010 0010 0010 0000 0010 0000 0000 1100 0001 0000 0011 0000 0001 0110 0001 1000

  29. Multiplication (version 3) • Product register has unused space • Large enough to hold the multiplier • As unused bits are filled • Multiplier requires less bits • Initialize product register • Zeros in the left half • Multiplier in the right half

  30. Multiplication (version 3)

More Related