The Microprocessor and its Architecture

1. The Microprocessor and its Architecture www.powerpointpresentationon.com

2. Intel Architecture Dr. Muhammad Nadeem

3. Programming Model Dr. Muhammad Nadeem

4. General-Purpose Registers • The top portion of the programming model contains the general purpose registers: EAX, EBX, ECX, EDX, EBP, ESI, and EDI. • These registers, although general in nature, each have special purposes and names. • EAX – Accumulator (as general as they come) used also as AX, AH, and AL • EBX – Base Index often used to address memory data (BX, BH, and BL) Dr. Muhammad Nadeem

5. General-Purpose Registers (continued) • ECX – count used in shifts and loops (CX, CH, and CL) • EDX – data used in multiply and divide (DX, DH, and DL) • EBP – base point used to address stack data (BP) • ESI – source index addresses memory data (SI) • EDI – destination index addresses memory data (DI) Dr. Muhammad Nadeem

6. Special-Purpose Registers • The special purpose register each have specific tasks and are ESP, EIP, and EFLAGS • ESP – address stack data used in functions (procedures) and temporary storage (SP) • EIP – addresses the next instruction in a program (IP) • EFLAGS – indicates conditions of the microprocessor (FLAGS) Dr. Muhammad Nadeem

7. EFLAGS Dr. Muhammad Nadeem

8. The Flags • C – holds a carry or a borrow • P – the parity flag (little use today) • A – auxiliary flag used with DAA and DAS • Z – zero • S – sign • O – Overflow • D – direction (used with string instructions) • I – interrupt (interrupt on/off) • T – trap flag (trace on/off) Dr. Muhammad Nadeem

9. Newer Flag Bits • IOPL – I/O privilege level for Windows • NT – nested task • RF – resume flag • VM – virtual mode • AC – alignment check • VIF – virtual interrupt (copy of interrupt flag) • VIP – virtual interrupt pending • ID = CPUID instruction available Dr. Muhammad Nadeem

10. Segment Register • The segment registers are: CS (code), DS (data), ES (extra), SS (stack), FS, and GS. • Segment registers address a section of memory in a program. A segment is either 64K in length (real mode) or up to 4G in length (protected mode). • All code (programs) reside in the code segment. Dr. Muhammad Nadeem

11. Default Segments for Offset address Dr. Muhammad Nadeem

12. Real Mode Memory Addressing • Real mode memory is the first 1M of the memory system. • All real mode addresses are a combination of a segment address plus an offset address. • The segment address (16-bits) is appended with a 0H or 00002 to form a 20-bit address. (or multiplied by 10H) • The effective address is this 20-bit segment address plus a 16-bit offset address. Dr. Muhammad Nadeem

13. Dr. Muhammad Nadeem

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15. Defaults • Default 16-bit addresses are programs in CS, stack data in SS, and most other data in a program in DS. • Default 32-bit addresses are programs in CS, stack data in SS and most other data in DS. • What’s the difference? 16-bit addresses use offset addresses in BX, SI, DI, BP, or an offset numeric value. 32-bit addresses use offset addresses in EAX, EBX, ECX, EDX, EBP, EDI, ESI or a numeric value. • Programs resides in segment CS addressed by IP/EIP • Stack data resides segment SS addressed by SP/ESP Dr. Muhammad Nadeem

16. Effective Address Calculations • EA = segment x 10H plus offset (a) 10023 = 10000 + 0023 (b) ABC34 = AAF00 + 0134 (c) 21FF0 = 12000 + FFF0 Example (a) contained 1000 in the segment register, example (b) contained a AAF0 in the segment register, and example (c) contained a 1200 in the segment register. Dr. Muhammad Nadeem

17. Relocation • Segment and offset addressing allows for easy and efficient relocation of code and data. • To relocate code or data only the segment number needs to be changed. For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of he instruction. Dr. Muhammad Nadeem

18. Protected Mode • The Windows operating system domain. • 4G of memory with 2G for the system and 2 G for the application • Protected mode still uses segment and offset addresses, but the offset address is 32-bits • Protection is provided by restricting access through priority levels and access rights Dr. Muhammad Nadeem

19. Descriptors describe memory • A descriptor is selected by the number placed in the segment register. • The descriptor describes the base address (starting address) and limit (offset to the ending address) of a segment. • The descriptor also defines the privilege level and access rights to a memory segment. Dr. Muhammad Nadeem

20. Dr. Muhammad Nadeem

21. The base address is a 32-bit address (Pentium class) that addresses the start of a memory segment. • The limit is a 20-bit number added to the base address to address the last address of a segment. • The limit has a modifier bit called Granularity (G) that select a multiplier of 4K for the limit (4K is 12-bits) (20-bits +12-bits is 32-bits) Dr. Muhammad Nadeem

22. base = 23000000H and a limit of 012FFH G = 0 Segment start = 23000000H Segment end = 230012FFH G = 1 (limit = 012FFFFFH) Segment start = 23000000H Segment end = 242FFFFFH Dr. Muhammad Nadeem

23. Access Rights Dr. Muhammad Nadeem

24. Segment Register Dr. Muhammad Nadeem

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26. Program Invisible Registers Dr. Muhammad Nadeem

27. Control Registers Dr. Muhammad Nadeem

28. Paging • The paging mechanism translates a logic address (address generated by the program) into a physical address (address that accesses a memory location). • It does this by sectioning the address into three parts: (1) directory, (2) page table, and (3) memory offset. • The directory and page table fields are each 10-bits wide and the memory offset is 12-bits. Dr. Muhammad Nadeem

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30. Dr. Muhammad Nadeem