2. Methods for I/O Operations

2. Methods for I/O Operations • Programmed I/O • Interrupt-Driven I/O • Direct Memory Access (DMA) • I/O Processors Input/Output Systems and Peripheral Devices (02-2)

Interrupt-Driven I/O • Principle of Interrupt-Driven I/O • Multiple-Interrupt Systems • Priority Interrupt Systems • Parallel Priority Interrupts • Daisy-Chain Priority Interrupts Input/Output Systems and Peripheral Devices (02-2)

Principle of Interrupt-Driven I/O (1) • Interrupt – suspension of program execution by an external signal or by an internal event of the CPU • Program suspension occurs at the end of the current instruction’s execution • The CPU is relieved from the task of testing the status of I/O devices • Interrupt sources can be external or internal to the CPU Input/Output Systems and Peripheral Devices (02-2)

Principle of Interrupt-Driven I/O (2) • Examples of interrupt sources: • Peripheral devices data transfers • Virtual memory page transfers • Hardware circuits for supervising normal operation of the system: detecting memory errors, power-supply failures • Internal software events: overflows, divisions by zero, non-existent or privileged instructions Input/Output Systems and Peripheral Devices (02-2)

Principle of Interrupt-Driven I/O (3) • For interrupting the CPU, a control line is asserted IREQ (Interrupt Request) • An interrupt flag is set • When recognizing the interrupt request, the CPU: • Asserts an interrupt acknowledge signal IACK (Interrupt Acknowledge) • Executes an interrupt handler routine, associated with the interrupt source Input/Output Systems and Peripheral Devices (02-2)

Principle of Interrupt-Driven I/O (4) • For transferring control to the interrupt handler routine: • The CPU identifies the interrupt source • The CPU determines the address of the interrupt handler corresponding to the interrupt source • The CPU saves the program counter (PC) and other status information • The CPU loads the address of the interrupt handlerinto the program counter Input/Output Systems and Peripheral Devices (02-2)

Principle of Interrupt-Driven I/O (5) • The CPU has to determine the address of the interrupt handler • Methods for choosing the address of the interrupt handler: • Nonvectored interrupts: the interrupt handler is located at a fixed address in memory • Vectored interrupts: the address is supplied by the interrupt source, in the form of an interrupt vector Input/Output Systems and Peripheral Devices (02-2)

Multiple-Interrupt Systems (1) • For registering the interrupt requests, an interrupt request register is used • For an individual control of interrupt sources, mask flip-flops are used interrupt mask register • Main problems: • Identifying the source of interrupt • Choosing the interrupt to service in case of several simultaneous requests Input/Output Systems and Peripheral Devices (02-2)

Multiple-Interrupt Systems (2) • Techniques foridentifying the source of interrupt: • Multiple interrupt lines • Software polling • Connecting the devices in a daisy chain (hardware polling) • Bus arbitration Input/Output Systems and Peripheral Devices (02-2)

Multiple-Interrupt Systems (3) • Multiple interrupt linesbetween the CPU and the I/O modules • The simplest solution • It is impractical to dedicate a large number of bus lines or processor pins to interrupt lines • Usually, multiple I/O modules will be attached to each line Input/Output Systems and Peripheral Devices (02-2)

Multiple-Interrupt Systems (4) • Software polling • When the CPU detects an interrupt, it executes an interrupt-service routine • The I/O modules are interrogated (polled) to determine which module generated the interrupt • For polling, a separate command linemay be used (e.g., TEST I/O) • Each I/O module may contain anaddressable status register Input/Output Systems and Peripheral Devices (02-2)

Multiple-Interrupt Systems (5) • Hardware polling • Adaisy-chain of devices is used • All I/O modules share a common interrupt request line • When detects an interrupt request, the CPU asserts an interrupt acknowledge signal • The interrupt acknowledge signal is daisy-chained through the I/O modules Input/Output Systems and Peripheral Devices (02-2)

Multiple-Interrupt Systems (6) • The acknowledge signal propagates through the I/O modules until it reaches a requesting module • This module responds byplacing an interrupt vector on the data bus • The CPU uses the vector as a pointer to the service routine for the module • Advantage: there is no need to execute a general interrupt service routine Input/Output Systems and Peripheral Devices (02-2)

Multiple-Interrupt Systems (7) • Bus arbitration • Uses vectored interrupts • An I/O modulemust first gain control of the bus before it can assert the interrupt request signal • When detects the interrupt, the CPU asserts the interrupt acknowledge signal • The requesting module places its vector on the data lines Input/Output Systems and Peripheral Devices (02-2)

Priority Interrupt Systems (1) • In case of simultaneous requests, a priority system is needed • Establishing the priority of simultaneous interrupts can be done in software or in hardware • Software method: • Identification of the highest-prioritysource is made by polling • There is acommon service routine, which polls the interrupt sources Input/Output Systems and Peripheral Devices (02-2)

Priority Interrupt Systems (2) • The order in which the sources are polled determines their priority • Disadvantage: if there are many sources, the time required for polling increases • Hardware method: • An interrupt controller accepts interrupt requests from many sources and determines the highest priority request • Each source has its own interrupt vector Input/Output Systems and Peripheral Devices (02-2)

Parallel Priority Interrupts (1) • An interrupt registerRINT is used • Its bits are set separately by the interrupt requests of each device • Priority is established according to the position of bits in the register • The interrupt mask registerRM allows to control (disable) the status of each interrupt request Input/Output Systems and Peripheral Devices (02-2)

Parallel Priority Interrupts (2) Input/Output Systems and Peripheral Devices (02-2)

Parallel Priority Interrupts (3) • The priority encoder: • Implements the priority function • Generates two bits of the interrupt vector • The vector is transferred to the CPU via tristate buffers • The buffers are enabled with the INTACK signal from the CPU and the IST, IEN flip-flops • IST – interrupt status flip-flop • IEN – interrupt enable flip-flop Input/Output Systems and Peripheral Devices (02-2)

Daisy-Chain Priority Interrupts (1) • All devices that can generate an interrupt request are connected in a daisy-chain • The device with the highest priority is placed in the first position • The interrupt request line is shared by all devices (wired OR connection) • When no interrupt requests are pending, the interrupt request line remains at logical 0 Input/Output Systems and Peripheral Devices (02-2)

Daisy-Chain Priority Interrupts (2) Input/Output Systems and Peripheral Devices (02-2)

Daisy-Chain Priority Interrupts (3) • The CPU responds to an interrupt request by asserting the INTACK signal • The signal is received by deviceD0 at its PI (Priority In) input • The signal is sent to the PO (Priority Out) output only if device D0 is not requesting an interrupt • If D0 has a pending interrupt: • Blocks the acknowledge signal • Places its own interrupt vector Input/Output Systems and Peripheral Devices (02-2)

Direct Memory Access (DMA) • Principle of I/O through DMA • Execution of DMA Transfers • Configurations of Systems Using DMA Transfers Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through DMA (1) • The disadvantage of programmed I/O and interrupt-driven I/O: the CPU is busy with managing the I/O operations • DMA eliminates this disadvantage  data transfers are executed directly between the internal memory and the I/O system • An additional module is required DMA controller • Two methods for performing transfers through DMA  Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through DMA (2) • By suspending the CPU operations and placing the bus in the high-impedance stateduring the transfer • Data breakor block transfer • This method is required, e.g., for magnetic disk drives  data transmission cannot be stopped or slowed down • The CPU is inactive for relatively long time periods Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through DMA (3) • By using the time intervals when the CPU does not access the memory • Cycle stealing • Large blocks of data are transferred by a sequence of DMA bus transactions interspersed with CPU bus transactions • The method reduces the maximum transfer rate, but it also reduces the interference of the DMA controller in accessing memory by the CPU Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through DMA (4) Breakpoints of the CPU for performing transfers through DMA and through interrupts Input/Output Systems and Peripheral Devices (02-2)

Execution of DMA Transfers (1) • The CPU sends an initialization sequence to the DMA controller • The initialization sequence contains: • Direction of transfer (read or write) • Address of the I/O device involved • Starting address of the memory area used for the transfer • Number of bytes or words to be transferred Input/Output Systems and Peripheral Devices (02-2)

Execution of DMA Transfers (2) • The CPU releases the bus and may execute other operations • The DMA controller generates the addresses and control signals needed for the transfer • After a DMA cycle, other cycles may follow or the control is transferred to the CPU • When the transfer is complete, the DMA controller generates aninterrupt request to the CPU Input/Output Systems and Peripheral Devices (02-2)

Execution of DMA Transfers (3) Input/Output Systems and Peripheral Devices (02-2)

Execution of DMA Transfers (4) • The CPU loads the IOAR and DC registers with initial values I/O instructions • When the DMA controller is ready for the transfer, it asserts the DMAREQsignal • At the next DMA breakpoint, the CPU releases the bus and asserts DMAACK • The DMA controller transfers data directly with the main memory;the IOAR and DC registers are updated Input/Output Systems and Peripheral Devices (02-2)

Execution of DMA Transfers (5) • If the DC register  0, but the I/O device is not ready, the DMA controller releases the bus • The CPU disables the DMAACK signal and takes control of the bus • If the DC register = 0, the DMA controller releases the bus and sends an interrupt request to the CPU • The CPU responds by halting the I/O device or by initiating a new transfer Input/Output Systems and Peripheral Devices (02-2)

Configurations of Systems Using DMA Transfers (1) Input/Output Systems and Peripheral Devices (02-2)

Configurations of Systems Using DMA Transfers (2) Input/Output Systems and Peripheral Devices (02-2)

I/O Processors • Principle of I/O through I/O Processors • Execution of an I/O Program • Intel I/O Processors Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through I/O Processors (1) • While DMAreleases the CPU from many I/O operations, for high-speed peripherals numerous bus cycles will be needed • During these cycles, the CPU enters a wait state • The cycle stealing will saturate the bus • A certain time is required to service the interrupts • The I/O modules have been improved, becoming I/O processors (IOPs) Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through I/O Processors (2) • Some of these I/O modules are also called I/O channels • IOPs have aspecialized instruction set for I/O operations • The CPU sends a command to the IOP to execute an I/O program(channel program) located in memory • The CPU can specify a sequence of I/O operations, and is interrupted only at the completion of the entire sequence Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through I/O Processors (3) Input/Output Systems and Peripheral Devices (02-2)

Principle of I/O through I/O Processors (4) • The CPU and IOP can also communicate with each other directly via controllines • DMA Request (DMAREQ) • DMA Acknowledge (DMAACK) • The CPU may attention the IOP by asserting the ATN (Attention) signal execution of an I/O program • The IOP may attention the CPU by asserting the IREQ signal execution of an interrupt service routine Input/Output Systems and Peripheral Devices (02-2)

Execution of an I/O Program Input/Output Systems and Peripheral Devices (02-2)

2. Methods for I/O Operations