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Lecture #32 Registers, counters etc.

Lecture #32 Registers, counters etc. Last lecture: Digital circuits with feedback Clocks Flip-Flops This Lecture: Edge triggers Registers shift registers counters. Edge triggering.

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Lecture #32 Registers, counters etc.

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  1. Lecture #32 Registers, counters etc. • Last lecture: • Digital circuits with feedback • Clocks • Flip-Flops • This Lecture: • Edge triggers • Registers • shift registers • counters EE 42 fall 2004 lecture 32

  2. Edge triggering • The last lecture ended with how a flip flop could be designed by using two latches which cascaded in a master-slave relationship. • Another way of creating an edge triggered flip flop is to use logic with feedback, as in the following slide. EE 42 fall 2004 lecture 32

  3. Edge-Triggered Flip-Flops • More efficient solution: only 6 gates • sensitive to inputs only near edge of clock signal (not while high) holds D' when clock goes low negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfullycapture input R Q Clk=1 Q’ S holds D whenclock goes low characteristic equationQ(t+1) = D D EE 42 fall 2004 lecture 32

  4. Edge-Triggered Flip-Flops (cont’d) • Positive edge-triggered • Inputs sampled on rising edge; outputs change after rising edge • Negative edge-triggered flip-flops • Inputs sampled on falling edge; outputs change after falling edge 100 D CLK Qpos Qpos' Qneg Qneg' positive edge-triggered FF negative edge-triggered FF EE 42 fall 2004 lecture 32

  5. Timing Methodologies • As we have seen, there are several different ways of designing a sequential logic circuit. In general, each circuit will stick with a set of rules which are designed to achieve consistently accurate results. • A set of rules for interconnecting components and clocks are adopted which will guarantee proper operation of system when strictly followed. • Approach depends on building blocks used for memory elements. Edge-triggered flip-flops are found in programmable logic devices • Many custom integrated circuits focus on level-sensitive latches EE 42 fall 2004 lecture 32

  6. Basic rules for correct timing: • Inputs to flip-flops are stable and correct for and interval around the time of sampling (avoid asynchronous inputs wherever possible) • No flip-flop changes state more than once per clocking event EE 42 fall 2004 lecture 32

  7. D D Q Q Tsu Th input clock Definition: Set up time/hold time data clock stable changing data clock To ensure that the data signal is captured accurately, the data must be stable for an time tsu (set up) before the edge, and kept constant for a time th (hold) after the edge. EE 42 fall 2004 lecture 32

  8. D Q D Q G Comparison of Latches and Flip-Flops D CLK Qedge Qlatch CLK positiveedge-triggeredflip-flop CLK transparent(level-sensitive)latch behavior is the same unless input changes while the clock is high EE 42 fall 2004 lecture 32

  9. Comparison of Latches and Flip-Flops (cont’d) TypeWhen inputs are sampledWhen output is valid unclocked always propagation delay from input changelatch level-sensitive clock high propagation delay from input changelatch (Tsu/Th around falling or clock edge (whichever is later) edge of clock) master-slave clock high propagation delay from falling edgeflip-flop (Tsu/Th around falling of clock edge of clock) negative clock hi-to-lo transition propagation delay from falling edgeedge-triggered (Tsu/Th around falling of clockflip-flop edge of clock) EE 42 fall 2004 lecture 32

  10. Typical Timing Specifications • Positive edge-triggered D flip-flop • Setup and hold times • Minimum clock width • Propagation delays Tsu0.8 ns Th0.5 ns D Tsu0.8 ns Th0.5 ns CLK Tw 1ns all measurements are made from the clocking event that is, the rising edge of the clock EE 42 fall 2004 lecture 32

  11. Q0 Q1 D D Q Q IN OUT CLK Cascading Edge-triggered Flip-Flops • Shift register • New value goes into first stage • While previous value of first stage goes into second stage • The propagation time must be longer than the hold time 100 IN Q0 Q1 CLK EE 42 fall 2004 lecture 32

  12. Cascading Edge-triggered Flip-Flops (cont’d) • Why this works • Propagation delays exceed hold times • Clock width constraint exceeds setup time • This guarantees following stage will latch current value before it changes to new value In Q0 Q1 CLK Tsu 4ns Tsu 4ns timing constraints guarantee proper operation of cascaded components Tp 3ns Tp 3ns assumes infinitely fast distribution of the clock Th 2ns Th 2ns EE 42 fall 2004 lecture 32

  13. Clock Skew • The problem • Correct behavior assumes next state of all storage elementsdetermined by all storage elements at the same time • This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic • Effect of skew on cascaded flip-flops: In Q0 Q1 CLK0 CLK1 100 CLK1 is a delayed version of CLK0 original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1 EE 42 fall 2004 lecture 32

  14. Summary of Latches and Flip-Flops • Development of D-Flip-Flop • Level-sensitive used in custom integrated circuits • can be made with 4 gates • Edge-triggered used in programmable logic devices • Good choice for data storage register • Historically J-K Flip Flop was popular but now never used • Similar to R-S but with 1-1 being used to toggle output (complement state) • Can always be implemented using D-FF • Preset and clear inputs are highly desirable on flip-flops • Used at start-up or to reset system to a known state EE 42 fall 2004 lecture 32

  15. Flip-Flop Features • Reset (set state to 0) – R • Synchronous: Dnew = R' • Dold (when next clock edge arrives) • Asynchronous: doesn't wait for clock, quick but dangerous • Preset or set (set state to 1) – S (or sometimes P) • Synchronous: Dnew = Dold + S (when next clock edge arrives) • Asynchronous: doesn't wait for clock, quick but dangerous • Both reset and preset • Dnew = R' • Dold + S (set-dominant) • Dnew = R' • Dold + R'S (reset-dominant) • Selective input capability (input enable/load) – LD or EN • Multiplexer at input: Dnew = LD' • Q + LD • Dold • Load may/may not override reset/set (usually R/S have priority) • Complementary outputs – Q and Q' EE 42 fall 2004 lecture 32

  16. Registers • Collections of flip-flops with similar controls and logic • Stored values somehow related (e.g., form binary value) • Share clock, reset, and set lines • Similar logic at each stage • Examples • Shift registers • Counters OUT1 OUT2 OUT3 OUT4 "0" R S R S R S R S D Q D Q D Q D Q CLK IN1 IN2 IN3 IN4 EE 42 fall 2004 lecture 32

  17. OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK Shift Register • Holds samples of input • Store last 4 input values in sequence • 4-bit shift register: EE 42 fall 2004 lecture 32

  18. Shift Register Application • Parallel-to-serial conversion for serial transmission parallel outputs parallel inputs serial transmission EE 42 fall 2004 lecture 32

  19. OUT OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK Pattern Recognizer • Combinational function of input samples • In this case, recognizing the pattern 1001 on the single input signal EE 42 fall 2004 lecture 32

  20. OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q CLK "1" Binary Counter • Logic between registers (not just multiplexer) • XOR decides when bit should be toggled • Always for low-order bit, only when first bit is true for second bit, and so on EE 42 fall 2004 lecture 32

  21. Sequential Logic Summary • Fundamental building block of circuits with state • R-S latch, R-S master/slave, D master/slave, edge-triggered D FF • Latch and flip-flop • Timing methodologies • Use of clocks • Cascaded FFs work because prop delays exceed hold times • Beware of clock skew • Asynchronous inputs and their dangers • Synchronizer failure: what it is and how to minimize its impact • Basic registers • Shift registers • Pattern detectors • Counters EE 42 fall 2004 lecture 32

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