A thesis by Giovanni Maria Anelli, Polytechnic of Grenoble

1. Conception et Caracterisation De Circuits Integres Resistants Aux Raditations Pour Les Detecteurs De Particules Du LHC En Technologies CMOS Submicroniques Profondes A thesis by Giovanni Maria Anelli, Polytechnic of Grenoble

2. Outline • Radiation effects in MOS transistors • Three Techniques for radiation tolerant design • Results from irradiated CMOS structures

3. here the general structure, single parts are then presented and discussed Trapped in the Oxide! Step 1: Ionizing particle creates electron hole pairs Step 2: Electron mobility >> Hole mobility, leaving holes trapped in the oxide. (Mobility factor of over 10^6)

4. Results of trapping Step 3: Threshold shifts due to new E field; increase in subthreshold/dark current. DOE money for a rapid fire structure, but future in push-pull operation many common problem needs to be solved (design, packaging, rad-hard)

5. Format for final detecor First Technique For Rad Tolerant Design • Hardening by System Architecture • Adding two feedback resistors eliminates single event flipping by increasing the RC constant.

6. Second Technique for Rad Tolerant Design • Hardening by layout • Enclosed Layout Transistor (ELT). No parasitic path from source to drain. Shown in example D.

7. Third Technique for Rad Tolerant Design • Hardening by design. • for 20nm< tox <100nm Vox ~ tox2 Vit~ toxn 0.5<n<2 • for tox<10 nm Vox ~ tox3 (electron tunneling) Vit~ tox3 After 1Mrad Vox ~ tox2 In deep submicron technologies Vt is not a problem! By Snoeys et al. NIMA

8. go tru functionality of each stage: integrate current, multiplex value tru cmos switch demultiplex to output amplifer each capacitor can be addressed independently Results of Second and Third Techniques OR • After 30 Mrad, almost no change in dark current of “smart” • transisitor using 0.25 um process and ELTs. • “Old style” transistor is in trouble. beam time structure increase count rate by 7

9. Matching transistors Systemic and environmental matching effects Matching for n-type ELTs shows greater degradation after 1.5 Mrad of 10 keV x-rays. It is not clear why this is the case.

10. Some Noise Characteristics1/f or flicker noisedue to random trapping and detrapping of carriers at the Si-SiO2 interface and within the gate oxidecheck 1/f noise parameter, Ka

11. Results of 1/f noise from irradiation: After annealing, Ka about the same for NMOS, still high for PMOS (explained by positive bias during annealing, i.e. Offshoot of annealing process)

12. An Analog Memory Circuit • A large array of capacitors to store analog values. Readout occurs when trigger is sent implying a “hit”.

13. Physical Layout of Circuit • Note ELTs on either side of the capacitor.

14. Storage of Analog Memory after Irradiation Results show that characteristics are virtually unchanged. Deviation from Vin, Vout

15. ALICE (A Large Ion Collider Experiment) Purpose: to study Quark Gluon Plasma. This environment accumulates a high radiation level over time. Solution: rad tolerant design! Need to read out detectors while in radiation environment.

16. Layout of ALICE detector readout chip

17. How does ALICE chip work? • Constantly stores values to memory. • When a hit is recorded, a trigger pulse dumps memory to ADCs then to disk. • This data is used to determine position information about the quark gluon plasma.

18. Results Well, it works. The author of the thesis provides absolutely no proof of this. He states, after showing five different characteristics of the chip, that upon irradiation it works the same way. Odd.