ECE 448: Lab 7 Design and Testing of an FIR Filter

ECE 448: Lab 7 Design and Testing of an FIR Filter

Finite Impulse Response (FIR) Filters FIR: Given an impulse input, the filter output goes to zero in a finite number of clocks because there is no feedback of the output to the input Filter: manipulate the frequency response Examples: low-pass, high-pass, band pass, notch, arbitrary Equation: • y : output • x : input • h : filter taps • (coefficients) • N : number of taps

Low Pass Filter

Parallel Architecture x[m] • Output every clock cycle • N multipliers (one per tap) • One N-input adder • N-stage shift register • (no reset!) • Constants h[i] stored • in registers or hardwired • Note the bit growth x[m-1] x[m-2] x[m-(N-1)] y[m]

Serial Architecture x[m] • Output every N clock • cycles • One multiplier • One 2-input adder • N-stage shift register • (no reset!) • Constants h[i] stored • in a single-port ROM • Multiplier-Accumulator (MAC) • Note the bit growth x[m-1] h[i] x[m-2] x[m-(N-1)] MAC y[m]

Parallel-Serial Architecture N/K-to-1 MUX x[m] • Output every N/K clock • cycles • K multipliers • One K+1 input adder • N-stage shift register • (no reset!) • Constants h[i] stored • in N/K single-port ROMs • Adder-Accumulator (AAC) • Note the bit growth ROM with N/K coefficients x[m-1] . . . x[m-2] . . . . ROM with N/K coefficients x[m-(N-1)] N/K-to-1 MUX AAC y[m]

Selected Architecture and Parameter Values • Parallel-Serial Architecture • N=256 • K=16 • L=M=18 • Clock frequency = 100 MHz

Lab 4 Top Level Numerically Controlled Oscillator Finite Impulse Response Filter

Task 1: Numerically Controlled Oscillator (NCO) Generator of digital samples 217 0 -217 Number of samples per period = 1024/(4step), where step = 1..63 Distance between samples = 391 clock periods = 3910 ns Amplitude = 217

Task 1: Numerically Controlled Oscillator (NCO) • Calculates numerical samples of the sinusoidal signal • f(t)=217sin(2πt/1024) with the frequency determined • by step=sw[5..0], which is in the range 0..63, and t • is a value of an accumulator incremented by • 4step every 391 clock cycles • Each sample is represented as an 18-bit signed integer • in the range from -2-17 to 217-1 • The total number of samples per period is given by • 1024/(4step) if step≠0, and 1 if step=0 • The distance between samples is equal to 391 clock periods = 3910 ns • Values of the function f(t)=217sin(2πt/1024) for t=0..1023 • stored in Block RAM

Task 1: Numerically Controlled Oscillator (NCO) • 6-bit Frequency Control Word (FCW) or step size • 10-bit accumulator: sum[n] = sum[n-1] + step*4, sum[0]=0 • 1024 18-bit signed sine values in a Lookup Table (LUT) • Accumulator addresses the LUT • Sine values stored in 1 Block RAM • Update every 391 clock cycles • valid pulse asserted for one clock cycle when output out • updated

Task 1: Numerically Controlled Oscillator (NCO) • Clock frequency of the oscillator: 1024 TOSC = 391TCLK 4step 4step fOSC = 100 MHz = step 0.999 KHz ≈ step 1 KHz 1024391

Task 1: Simulating Analog Signals • Change the signal property in ModelSim to: • Show the waveform in analog form • Change the height of the analog waveform • Change the radix of the signal to signed or unsigned

Task 2: Filter • 256-tap FIR Filter using Parallel-Serial Architecture • K=16 18x18 Multipliers • N=256 samples stored in a 256-stage shift register • Taps stored in K=16 single-port ROMs of the size • N/K x 18 = 16 x 18 • Starts processing when valid input is high • Generates a valid output pulse

Task 3: Magnitude, Scale, Moving Average • Calculates when valid is high • Magnitude: magnitude = abs(in) • Scale: scale = magnitude / 2^28 • Moving Average: • Store 1024 of the most recent scaled values in circular buffer acting as a shift-register. • Implement circular buffer using a 1024x16 Block RAM using CORE Generator • sum[n] = sum[n-1] + scale[n] - scale[n-1024] • Don’t forget to account for the accumulator bit growth • avg = sum / 2^10

Task 3: Magnitude, Scale, Moving Average g(t)=abs(FIR(f(t)) Average Magnitude 0 FIR(f(t)) is an output from the filter Average Magnitude large if f(t) passed by the filter Average Magnitude small if f(t) attenuated by the filter

Task 4: Seven Segment Display

Task 5: Filter Select • Switch[7:6] selects one of four filters in the Tap Buffer • Sketch the frequency response of each filter

Task 5: Tap ROMs 0 15 16 31 32 64 deep 47 48 63

Task 6: Digital-to-Analog Converter 8 pmod[7..0] • Generates analog signal to show on oscilloscope • Convert signed to biased unsigned (ex: [-128:127] to [0:255]) • Button[0] cycles between the NCO, Filter, and Magnitude • NCO selected: out = nco / 2^10 and LED[0] on • Filter selected: out = filter / 2^36 and LED[1] on • Magnitude selected: out = mag / 2^36 and LED[2] on

8-Bit Parallel Digital-to-Analog Converter (DAC) • PMOD-R2R • http://www.digilentinc.com

PMOD Pins on Board NET "PMOD<0>" LOC = "T12" | IOSTANDARD = LVTTL ; NET "PMOD<1>" LOC = "V12" | IOSTANDARD = LVTTL ; NET "PMOD<2>" LOC = "N10" | IOSTANDARD = LVTTL ; NET "PMOD<3>" LOC = "P11" | IOSTANDARD = LVTTL ; NET "PMOD<4>" LOC = "M10" | IOSTANDARD = LVTTL ; NET "PMOD<5>" LOC = "N9" | IOSTANDARD = LVTTL ; NET "PMOD<6>" LOC = "U11" | IOSTANDARD = LVTTL ; NET "PMOD<7>" LOC = "V11" | IOSTANDARD = LVTTL ;

Switch and Buttons Functions • Switch[5:0] NCO Frequency Control Word (step) • Used in NCO and Shape Generator • Switch[7:6] Filter Select • Button[0] DAC Select • NCO • Filter • Magnitude

CORE Generator Demonstration

ECE 448: Lab 7 Design and Testing of an FIR Filter