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ARM Cortex-M0

ARM Cortex-M0. CORTEX-M0 Structure Discussion 3. August 23, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. www.orchid-tech.com. Cortex-M0 Structure Discussion 3. Topics Today CORTEX-M0 Power Management CORTEX-M0 Fault Handling CORTEX-M0 Stack Structures

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ARM Cortex-M0

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  1. ARM Cortex-M0 CORTEX-M0 Structure Discussion 3 August 23, 2012Paul NickelsbergOrchid Technologies Engineering and Consulting, Inc.www.orchid-tech.com

  2. Cortex-M0 Structure Discussion 3 Topics Today • CORTEX-M0 Power Management • CORTEX-M0 Fault Handling • CORTEX-M0 Stack Structures • CORTEX-M0 SVC/WFE/WFI Instructions

  3. Cortex-M0 Power Management Our discussion focuses on Cortex-M0 Power Managementas distinct from additional power management features which may be implemented by a particular device vendor

  4. Cortex-M0 Power Management Low Power Instruction Execution Approx Current in mA Approx Speed in MHz

  5. Cortex-M0 Power Management Cortex-M0 Power Modes • Sleep ModeStops Processor Clock • Deep Sleep ModeStops System Clock, Power off PLL, and Memory • Mode Selection made using SCB Register

  6. Cortex-M0 Power Management Cortex-M0 Entry into Power Saving Modes • WFI InstructionExecution of WFI Instruction causes processor to immediately enter selected sleep mode • WFE InstructionExecution of WFE Instruction causes processor to enter selected sleep mode if event bit is set • Exit Processor ExceptionIf SLEEPONEXIT bit is set in SCB Register, processor enters selected sleep mode on return from exception to thread mode

  7. Cortex-M0 Power Management Cortex-M0 Exit from Power Saving Modes • Wake-Up from WFI or SLEEPONEXITUpon receipt of Prioritized Interrupt, processor immediately resumes execution of instructions • Wakeup from WFEUpon receipt of Prioritized Interrupt or external event signal, processor immediately resumes execution of instructions • Wakeup using WICUpon receipt of Wake-up Interrupt Controller Signal, processor immediately resumes execution of instruction. This feature is optional and when implemented usually applies to Deep Sleep wakeup only

  8. Cortex-M0 Power Management Full Pwr Low Pwr Time IRQ WFI Normal Instruction Execution Sleep Normal Instruction Execution

  9. Cortex-M0 Fault Handling • HARDFAULT VectorThe HARDFAULT Vector catches processor faults • Processor Faults • SVC Instruction Priority Error • BKPT w/o Debugger • System Generated Bus Error • Attempted execution of instruction in XN Memory Area • Attempted execution of undefined instruction • Attempted load or store to unaligned address • Processor Lockup (Double Fault)Occurs when Fault occurs in NMI or HARDFAULT Handler

  10. Cortex-M0 Fault Handling RESET Bad Instruction Bad Instruction HardFault Normal Instruction Execution Normal Instruction Execution Lock Up HardFault Exception preempts all other exceptions Reset or NMI restarts processor

  11. Cortex-M0 Stack Structure • Cortex-M0 Stack pushes data onto the stack from higher to lower addresses SP Here before Interrupt SP Here after Interrupt

  12. Meaning and Implications 32 Bit CORTEX-M0 Processing Capability - Low Power Instruction Execution - Sleep Power Mode - Deep Sleep Power Mode - WFI / WFE Sleep Entry - Fault Handling 8 Bit Architecture Processor Architecture – 8 Bit World to 32 Bit World

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