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Calorimeter upgrade meeting – CERN – October 5 th 2010

Analog FE ASIC: first prototype Upgrade of the front end electronics of the LHCb calorimeter. E. Picatoste , A. Sanuy, D. Gascón Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB. Calorimeter upgrade meeting – CERN – October 5 th 2010. Outline. Introduction

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Calorimeter upgrade meeting – CERN – October 5 th 2010

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  1. Analog FE ASIC: first prototype Upgrade of the front end electronics of the LHCb calorimeter E. Picatoste, A. Sanuy, D. Gascón Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB Calorimeter upgrade meeting – CERN – October 5th 2010

  2. Outline • Introduction • Current Mode Preamplifier • Integrator • FDOA • Switched Integrator • Linearity • Noise • IC Implementation Details LHCb Upgrade

  3. Introduction • ECAL analogue FE IC: channel architecture Switched integrator Track and Hold First Prototype LHCb Upgrade

  4. Introduction • IC sent: ICECAL Current preamp Integrators LHCb Upgrade

  5. Current mode preamplifier Inner loop: lower input impedance Outer loop: control input impedance • Pros: • “Natural” current processing • Lower supply voltage • All low impedance nodes: • Pickup rejection • No external components • No extra pad • Cons: • Trade-off in current mirrors: linearity vs bandwidth • Low voltage • Only 1 Vbe for the super common base input stage • Better in terms of ESD: • No input pad connected to any transistor gate or base LHCb Upgrade

  6. Current mode preamplifier Possible compensations: • Parallel R • current ladder • Simulations based on the extracted RC |Zin| Zin phase Gain+ |Gain| Gain- Gain- Gain phase Gain+ LHCb Upgrade

  7. Current mode preamplifier • Simulations based on the extracted RC: linearity vs. Ii,peak Gain- Gain+ Operation range LHCb Upgrade

  8. Current mode preamplifier • Linearity error after integration (ideal) vs input charge LHCb Upgrade

  9. Integrator • Switched integrator architecture FDOA CMOS switches LHCb Upgrade

  10. FDOA: design Common Mode Feedback • Fully differential Operational Amplifier Folded cascode NPN CE amp RDegenertion Pole compensation LHCb Upgrade

  11. FDOA: open loop post layout simulations • IbCE = 900uA • Load capacitor between 150fF and 5.1pF GLF (dB) BW (KHz) G (dB) GBW (MHz) Phase (º) PM (º) LHCb Upgrade

  12. FDOA: closed loop post layout simulations • IbCE = 900uA • Load capacitor between 150fF and 5.1pF trise (ns) overshoot SR (V/ns) LHCb Upgrade

  13. Integrator: pulse response • Simulations based on extracted RC • Cl = 5pF Vout (V) Vint,ideal (V) Iin (mA) ViD (mV) LHCb Upgrade

  14. Integrator: Linearity • Simulations based on extracted RC • Cl = 5pF Error (%) Vout (V) LHCb Upgrade

  15. Front End simulations (Preamp+integrator) • Simulations based on extracted RC of complete IC • Includes PM signal (TDR) and cable effects PM signal cable Preamp + integrator Clipping line LHCb Upgrade

  16. Front End simulation (Preamp+integrator) • Simulations based on extracted RC of complete IC • Includes PM signal (TDR) and cable effects VPM VoD2 VoD1 Icable (clipped) IPM Vi LHCb Upgrade

  17. Front End simulation: linearity Dynamic deviation of the input impedance LHCb Upgrade

  18. Front End simulation: linearity VoD1 Linear error VoD2 LHCb Upgrade

  19. Front End simulation: noise Noise σ = 377 μV Noise after dynamic pedestal subtraction σ = 479 μV Sampling time t1 • Transient noise analysis Sampling time t2 Integrator 1 output Clock Noise at output: distribution of V(t2) Noise after dynamic pedestal subtraction: distributon of V(t1)- V(t2) LHCb Upgrade

  20. IC Implementation details Downbond • AMS SiGe BiCMOS s35 • QFN package • Substrate connected to central pad (gnd) • When taking into account the bonding parasistics: • 3 * nominal L ⇒ danger of ringing • Solutions: • Include R in series with decoupling capacitor of Vref • Increase number of gnd pins • Downbonds for gnd LHCb Upgrade

  21. Prototype test PCB • PCB designed for tests • 4 layers • 2 socket compatible • About 8x9 cm • Chips arrived on 1st October. LHCb Upgrade

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