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CENTRE FOR FORMAL DESIGN AND VERIFICATION OF SOFTWARE

CENTRE FOR FORMAL DESIGN AND VERIFICATION OF SOFTWARE. INDIAN INSTITUTE OF TECHNOLOGY, BOMBAY. Verification & Validation (V&V). Computers everywhere Safety-critical Systems Aircrafts, Trains, Nuclear & Industrial Plants, Avionics Life Support Systems Quality of Computational Systems

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CENTRE FOR FORMAL DESIGN AND VERIFICATION OF SOFTWARE

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  1. CENTRE FOR FORMAL DESIGN AND VERIFICATION OF SOFTWARE INDIAN INSTITUTE OF TECHNOLOGY, BOMBAY

  2. Verification & Validation (V&V) • Computers everywhere • Safety-critical Systems • Aircrafts, Trains, Nuclear & Industrial Plants, Avionics • Life Support Systems • Quality of Computational Systems = Quality of life

  3. Bugs are costly • Pentium bug • Intel Pentium chip, released in 1994 produced error in floating point division • Cost : $475 million • ARIANE Failure • In December 1996, the Ariane 5 rocket exploded 40 seconds after take off . A software components threw an exception • Cost : $400 million payload. • Therac-25 Accident : • A software failure caused wrong dosages of x-rays. • Cost: Human Loss. Rigorous V&V Essential

  4. Traditional V & V • Industrial Practices far from satisfactory • Testing, Simulation, Reviews & Walkthroughs • Inadequate for safety-critical systems • Late Detection of bugs • Detects presence of bugs not absence • When to stop testing • Coverage criteria • ~70% of time spent on V&V

  5. R & D Resources V & V Ed.&Tr. Mission of CFDVS

  6. The Mission • To Enable, through R&D of new tools andTechniques, • to Supportthrough external projects, • to Educate to develop skill base • through courses & workshops • to Develop Resource Baseof tools, technologies,standards • RIGOROUS DESIGN, V & V PRACTICES

  7. CFDVS Focus Area • V & V based on Formal Methods • Safety-critical Systems • Hardware & Software • Industrial Solutions

  8. Formal Verification • More rigorous approach • Founded on Mathematical methods • Proves correctness of Systems • Increased confidence • Early Detection of bugs • Design Verification • Complementary to traditional techniques

  9. CFDVS – An R&D Centre • Research Projects • Case-studies • New Tools • Efficient Techniques and Novel Design Methodologies

  10. CFDVS – A Resource Centre • Specification & Verification Tools • Academic & Commercial Tools • Books, Papers & Reports • Hardware & Software support • V&V Expert consultancy • National Centre

  11. CFDVS – An Educational Centre • Education & Training • Courses & Seminars • Workshops & Conferences • Student Projects & Case studies

  12. Resources Hardware : • Dec Alpha server • Sun server Sun-Fire 280R • Many access stations Software: • Formal Check: Hardware Verification Tool(Cadence Inc.) • LDRA : Static analysis tool • Rose RT and Rhapsody : UML based tools • Esterel Studio and SCADE • Specman: Hardware Verification tool • Code Surfer: Slicing tool

  13. Resources (contd.) Books : • More than hundred books/proceedings • CAV, FMCAD, CHARME

  14. Education and Training • Attracted many students across different departments (CSE,IT,EE,Rel. Engg.) • Around 30 students (B.Tech and M.Tech) completed • More than 10 students currently working • Two BARC staff on deputation • Two workshops • Well-attended • People from DAE and other organization • Tutorials in international conferences

  15. Industry Sponsored Projects • IV & V services • Two projects completed • Two more projects in Progress • Looking forward to more • Means of Resource Generation

  16. Formal Verification of Flight Software: Sponsor : ADA , Bangalore • Validation of software in LCA display unit • Verification focused on a collection of C-functions • In house tool ACE extensively used (jointly developed with BARC) • Verification engine : STeP • Verification uncovered a few bugs leading to code revision • Designers convinced of utility of FV

  17. Verification of Cache controllers Sponsor : Texas Instruments, Bangalore • Verification using Model Checking of medium sized industrial design. • Cache controller developed at TI, • FormalCheck of Cadence Inc. - verifier

  18. Verification of LV Software • LV – Launch Vehicle • Sponsored by VSSC, Trivandrum • Signal integrity checking • Complex sequence of branches • Code in Ada • In-house tool ACE used

  19. Verification of In-house ASICs Sponsor : BARC • Various ASICs designed at BARC • Verification of one of these • Project in the initial stages

  20. CFDVS R&D Overview • Case-studies • Tools • ACE • TSCheck • ConSDE • VE-DAC • EX-PERT • Research Papers and Reports

  21. Case-Studies • FV of Two Systems from BARC • FV of a PCI implementation

  22. FV of PCI implementation • Understand issues involved in large hardware design • Evaluate the performance of state-of-the art tools • PCI implementation (10,000 lines of VHDL code) • The tool Formal Check used • Models for environment designed • Properties formalized in FQL

  23. ACE – Assertion checker • Assertion-checking tool for formal verification of C-Programs • Translates C functions plus assertions to SPL and specifications • Verification of SPL programs • STeP – Verification Engine • Tool extensively used in ADA project

  24. Design Environment for Process Control Software • ConSDE: A tool for designing process control software from high level block diagrams • A graphical editor • A block definition language • Code generation from blocks • Simulation capabilities • Verification capabilities planned

  25. Verification Environment for distributed Control Applications • VE-DAC and EX-PERT: Tool for verification of distributed reactive applications. • State machine based language • Capabilities to design concurrent and hierarchical design • Asynchronous communication • Editor, simulator and verifier • Efficient verification using slicing techniques

  26. Probabilistic Interface Timing Verification • Efficient computation of • Bounds on the probability of violation of timing requirements • Bounds on performance metrics of the aggregate system • Given statistical information about component delays and the timing requirements of ckts • A dynamic programming algorithm • A polynomial time algorithm • implemented and tested on some benchmarks • bounds are fairly accurate in practice

  27. Timing Analysis and Verification of Gate-level Asynchronous Circuits • detect potential timing violations in a timed Asynchronous circuit • Useful for timing verification of practical timed ckts. • Polynomial-time algorithm for accurate detection of transition ordering • Algorithm to compute delay parameters of generalized C-elements • Algorithms faster than simulation using SPICE or IRSIM

  28. . . . And many more Projects • Efficient Verification of Synchronous Programs • Model-based Verification of Object-Oriented Software • Slicing of Synchronous Programs and HDLs

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