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TITLE ASSEMBLY LANGUAGE DEFINITION FILE FOR UP1 COMPUTER DESIGN WORD 16 WIDTH 72 LINES 50

TITLE ASSEMBLY LANGUAGE DEFINITION FILE FOR UP1 COMPUTER DESIGN WORD 16 WIDTH 72 LINES 50 ;****************************************************************** ; INSTRUCTION OPCODE LABELS - MUST BE 8-BITS, 2 Hex DIGITS ;******************************************************************

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TITLE ASSEMBLY LANGUAGE DEFINITION FILE FOR UP1 COMPUTER DESIGN WORD 16 WIDTH 72 LINES 50

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  1. TITLE ASSEMBLY LANGUAGE DEFINITION FILE FOR UP1 COMPUTER DESIGN WORD 16 WIDTH 72 LINES 50 ;****************************************************************** ; INSTRUCTION OPCODE LABELS - MUST BE 8-BITS, 2 Hex DIGITS ;****************************************************************** LADD: EQU H#00 LSTORE: EQU H#01 LLOAD: EQU H#02 LJUMP: EQU H#03 LJNEG: EQU H#04 LSUB: EQU H#05 LXOR: EQU H#06 LOR: EQU H#07 LAND: EQU H#08 LJPOS: EQU H#09 LZERO: EQU H#0A LADDI: EQU H#0B LSHL: EQU H#0C LSHR: EQU H#0D LIN: EQU H#0E LOUT: EQU H#0F LWAIT: EQU H#10

  2. ;******************************************************************;****************************************************************** ; DATA PSEUDO OPS ;****************************************************************** ;DB: DEF 8VH#00 ;8-BIT DATA DIRECTIVE DW: DEF 16VH#0000 ;16-BIT DATA DIRECTIVE ;****************************************************************** ;ASSEMBLY LANGUAGE INSTRUCTIONS ;****************************************************************** ADD: DEF LADD,8VH#00 STORE: DEF LSTORE,8VH#00 LOAD: DEF LLOAD,8VH#00 JUMP: DEF LJUMP,8VH#00 JNEG: DEF LJNEG,8VH#00 SUBT: DEF LSUB,8VH#00 XOR: DEF LXOR,8VH#00 OR: DEF LOR,8VH#00 AND: DEF LAND,8VH#00 JPOS: DEF LJPOS,8VH#00 ZERO: DEF LZERO,8VH#00 ADDI: DEF LADDI,8VH#00 SHL: DEF LSHL,H#0,4VH#0 SHR: DEF LSHR,H#0,4VH#0 IN: DEF LIN,8VH#00 OUT: DEF LOUT,8VH#00 WAIT: DEF LWAIT,8VH#00 END

  3. TITLE EXAMPLE UP1 COMPUTER ASSEMBLY LANGUAGE TEST PROGRAM LIST F,W LINES 50 ;********************************* ; MACROS ;********************************* ECHO: MACRO PORT IN PORT OUT PORT ENDM ;********************************* ; CONSTANTS ;********************************* CON1: EQU 2 DISPLAY: EQU H#00 SWITCH: EQU H#01 ;********************************* ; PROGRAM AREA ;********************************* ORG H#00 START: LOAD LABEL1%: ADDI 1%: SHL 1 SHR CON1%: AND H#0F OR H#80 SUBT LABEL2%: JPOS ENDP%: XOR LABEL3%: ADD (TABLE1 + 3)%: JNEG ENDP%: IN SWITCH OUT DISPLAY

  4. ; MACRO TEST ECHO H#10 WAIT B#11000011 ENDP: STORE LABEL1%: LOOP: JUMP LOOP%: JUMP START<%: JUMP $%: ;******************************** ; DATA FOR TEST PROGRAM ;******************************** ORG H#80 LABEL1: DW H#0ACE LABEL2: DW H#0000 LABEL3: DW H#FFFF ;UNSIGNED LARGEST NUMBER LABEL4: DW H#7FFF ;TWO'S COMPLEMENT LARGEST NUMBER TABLE1: DW H#0000 DW H#0011 DW H#0022 DW H#0033 DW H#0044 DW H#0055 DW H#0066 DW H#0077 DW H#0088 END

  5. Addr Line EXAMPLE UP1 COMPUTER ASSEMBLY LANGUAGE TEST PROGRAM 1 TITLE EXAMPLE UP1 COMPUTER ASSEMBLY LANGUAGE TEST PROGRAM 2 LIST F,W 3 LINES 50 4 ;********************************* 5 ; MACROS 6 ;********************************* 7 ECHO: MACRO PORT 8 IN PORT 9 OUT PORT 10 ENDM 11 ;********************************* 12 ; CONSTANTS 13 ;********************************* 14 CON1: EQU 2 15 DISPLAY: EQU H#00 16 SWITCH: EQU H#01 17 ;********************************* 18 ; PROGRAM AREA 19 ;*********************************

  6. 00000 20 ORG H#00 00000 0280 21 START: LOAD LABEL1%: 00001 0B01 22 ADDI 1%: 00002 0C01 23 SHL 1%: 00003 0D02 24 SHR CON1%: 00004 080F 25 AND H#0F 00005 0780 26 OR H#80 00006 0581 27 SUBT LABEL2%: 00007 0910 28 JPOS ENDP%: 00008 0682 29 XOR LABEL3%: 00009 0087 30 ADD (TABLE1 + 3)%: 0000A 0410 31 JNEG ENDP%: 0000B 0E01 32 IN SWITCH 0000C 0F00 33 OUT DISPLAY 34 ; MACRO TEST 35 ECHO H#10 0000D 0E10 35 + IN H#10 0000E 0F10 35 + OUT H#10 35 + ENDM 0000F 10C3 36 WAIT B#11000011 00010 0180 37 ENDP: STORE LABEL1%: 00011 0311 38 LOOP: JUMP LOOP%: 00012 0300 39 JUMP START%: 00013 0313 40 JUMP $%:

  7. 41 ;******************************** 42 ; DATA FOR TEST PROGRAM 43 ;******************************** 00080 44 ORG H#80 00080 0ACE 45 LABEL1: DW H#0ACE 00081 0000 46 LABEL2: DW H#0000 00082 FFFF 47 LABEL3: DW H#FFFF ;UNSIGNED LARGEST NUMBER 00083 7FFF 48 LABEL4: DW H#7FFF ;TWO'S COMPLEMENT LARGEST NUMBER 00084 0000 49 TABLE1: DW H#0000 00085 0011 50 DW H#0011 00086 0022 51 DW H#0022 00087 0033 52 DW H#0033 00088 0044 53 DW H#0044 00089 0055 54 DW H#0055 0008A 0066 55 DW H#0066 0008B 0077 56 DW H#0077 0008C 0088 57 DW H#0088 58 END

  8. S t a t e D i a g r a m R e s e t A 0 X 1 X X 1 C B O u t p u t 1 X 0

  9. m o d u l e s t a t e _ m a c h ( c l k , r e s e t , i n p u t 1 , e n t i t y s t a t e _ m a c h i s i n p u t 2 , o u t p u t 1 ) ; p o r t ( c l k , r e s e t : i n s t d _ l o g i c ; i n p u t c l k , r e s e t , i n p u t 1 , i n p u t 2 ; i n p u t 1 , i n p u t 2 : i n s t d _ l o g i c ; o u t p u t o u t p u t 1 ; 0 u t p u t 1 : o u t s t d _ l o g i c ) ; r e g o u t p u t 1 ; e n d s t a t e _ m a c h ; r e g [ 1 : 0 ] s t a t e ; a r c h i t e c t u r e A o f s t a t e _ m a c h i s p a r a m e t e r [ 1 : 0 ] s t a t e _ A = 0 , s t a t e _ B = 1 , t y p e S T A T E _ T Y P E i s ( s t a t e _ A , s t a t e _ B , s t a t e _ C ) ; s t a t e _ C = 2 ; s i g n a l s t a t e : S T A T E _ T Y P E ; a l w a y s @ ( p o s e d g e c l k o r p o s e d g e r e s e t ) b e g i n b e g i n p r o c e s s ( r e s e t , c l k ) i f ( r e s e t ) b e g i n s t a t e = s t a t e _ A ; i f r e s e t = ' 1 ' t h e n e l s e s t a t e < = s t a t e _ A ; c a s e ( s t a t e ) e l s i f c l k ' E V E N T a n d c l k = ' 1 ' t h e n s t a t e _ A : c a s e s t a t e i s i f ( i n p u t 1 = = 0 ) w h e n s t a t e _ A = > s t a t e = s t a t e _ B ; i f i n p u t 1 = ' 0 ' t h e n e l s e s t a t e < = s t a t e _ B ; s t a t e = s t a t e _ C ; e l s e s t a t e _ B : s t a t e < = s t a t e _ C ; s t a t e = s t a t e _ C ; e n d i f ; s t a t e _ C : w h e n s t a t e _ B = > i f ( i n p u t 2 ) s t a t e < = s t a t e _ C ; s t a t e = s t a t e _ A ; w h e n s t a t e _ C = > e n d c a s e i f i n p u t 2 = ' 1 ' t h e n e n d s t a t e < = s t a t e _ A ; a l w a y s @ ( s t a t e ) e n d i f ; b e g i n e n d c a s e ; c a s e ( s t a t e ) e n d i f ; s t a t e _ A : o u t p u t 1 = 0 ; e n d p r o c e s s ; s t a t e _ B : o u t p u t 1 = 0 ; w i t h s t a t e s e l e c t s t a t e _ C : o u t p u t 1 = 1 ; o u t p u t 1 < = ' 0 ' w h e n s t a t e _ A , d e f a u l t : o u t p u t 1 = 0 ; ' 0 ' w h e n s t a t e _ B , ' 1 ' w h e n s t a t e _ C , ' 0 ' w h e n o t h e r s ; e n d a ; V H D L S t a t e M a c h i n e M o d e l V e r i l o g S t a t e M a c h i n e M o d e l e n d c a s e e n d e n d m o d u l e

  10. A L U B l o c k D i a g r a m B i n p u t A i n p u t 1 6 1 6 A L U A L U _ c o n t r o l ( 2 . . 1 ) + , - , A N D , O R A L U _ o u t p u t 1 6 A L U _ c o n t r o l ( 0 ) S h i f t L e f t 1 6 C l o c k R e g i s t e r 1 6 R e g _ o u t p u t

  11. V e r i l o g M o d e l o f A L U V H D L M o d e l o f A L U m o d u l e A L U ( A L U _ c o n t r o l , A i n p u t , B i n p u t , e n t i t y A L U i s C l o c k , R e g _ o u t p u t ) ; p o r t ( A L U _ c o n t r o l : i n s t d _ l o g i c _ v e c t o r ( 2 d o w n t o 0 ) ; i n p u t [ 2 : 0 ] A L U _ c o n t r o l ; A i n p u t , B i n p u t : i n s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; i n p u t [ 1 5 : 0 ] A i n p u t ; C l o c k : i n s t d _ l o g i c ; i n p u t [ 1 5 : 0 ] B i n p u t ; R e g _ o u t p u t : o u t s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ) ; i n p u t C l o c k ; e n d A L U ; o u t p u t [ 1 5 : 0 ] R e g _ o u t p u t ; r e g [ 1 5 : 0 ] R e g _ o u t p u t ; a r c h i t e c t u r e R T L o f A L U i s r e g [ 1 5 : 0 ] A L U _ o u t p u t ; s i g n a l A L U _ o u t p u t : s t d _ l o g i c _ v e c t o r ( 1 5 d o w n t o 0 ) ; b e g i n a l w a y s @ ( A L U _ c o n t r o l o r A i n p u t o r B i n p u t ) p r o c e s s ( A L U _ C o n t r o l , A i n p u t , B i n p u t ) b e g i n c a s e ( A L U _ c o n t r o l [ 2 : 1 ] ) c a s e A L U _ C o n t r o l ( 2 d o w n t o 1 ) i s 0 : A L U _ o u t p u t = A i n p u t + B i n p u t ; w h e n " 0 0 " = > A L U _ o u t p u t < = A i n p u t + B i n p u t ; 1 : A L U _ o u t p u t = A i n p u t - B i n p u t ; w h e n " 0 1 " = > A L U _ o u t p u t < = A i n p u t - B i n p u t ; 2 : A L U _ o u t p u t = A i n p u t & B i n p u t ; w h e n " 1 0 " = > A L U _ o u t p u t < = A i n p u t a n d B i n p u t ; 3 : A L U _ o u t p u t = A i n p u t | B i n p u t ; w h e n " 1 1 " = > A L U _ o u t p u t < = A i n p u t o r B i n p u t ; d e f a u l t : A L U _ o u t p u t = 0 ; w h e n o t h e r s = > A L U _ o u t p u t < = e n d c a s e " 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 " ; e n d c a s e ; e n d p r o c e s s ; p r o c e s s a l w a y s @ ( p o s e d g e C l o c k ) b e g i n i f ( A L U _ c o n t r o l [ 0 ] = = 1 ) w a i t u n t i l r i s i n g _ e d g e ( C l o c k ) ; R e g _ o u t p u t = A L U _ o u t p u t < < 1 ; i f A L U _ c o n t r o l ( 0 ) = ' 1 ' t h e n e l s e R e g _ o u t p u t < = A L U _ o u t p u t ( 1 4 d o w n t o 0 ) & " 0 " ; R e g _ o u t p u t = A L U _ o u t p u t ; e l s e e n d m o d u l e R e g _ o u t p u t < = A L U _ o u t p u t ; e n d i f ; e n d p r o c e s s ; e n d R T L ; 1 6

  12. //Simple Computer Design from Chapter 8 in Verilog module SCOMP (clock,reset,program_counter,register_A, memory_data_register_out, instruction_register); input clock,reset; output [7:0] program_counter; output [15:0] register_A, memory_data_register_out, instruction_register; reg [15:0] register_A, instruction_register; reg [7:0] program_counter; reg [3:0] state; reg [7:0] memory_address_register; reg memory_write; // State Encodings parameter reset_pc = 0, fetch = 1, decode = 2, execute_add = 3, execute_store = 4, execute_store2 = 5, execute_store3 = 6, execute_load = 7, execute_jump = 8; wire [15:0] memory_data_register; wire [15:0] memory_data_register_out = memory_data_register; wire [15:0] memory_address_register_out = memory_address_register; wire memory_write_out = memory_write;

  13. // Use LPM function for computer's memory (256 16-bit words) LPM_RAM_DQ LPM_RAM_DQ_component( .address (memory_address_register_out), .inclock (clock), .data (register_A), .we (memory_write_out), .q (memory_data_register)); defparam LPM_RAM_DQ_component.LPM_WIDTH = 16, LPM_RAM_DQ_component.LPM_WIDTHAD = 8, LPM_RAM_DQ_component.LPM_INDATA = "REGISTERED", LPM_RAM_DQ_component.LPM_ADDRESS_CONTROL = "UNREGISTERED", LPM_RAM_DQ_component.LPM_OUTDATA = "UNREGISTERED", LPM_RAM_DQ_component.USE_EAB = "ON", // Reads in mif file for initial program and data values LPM_RAM_DQ_component.LPM_FILE = "program.mif";

  14. always@(posedge clock or posedge reset) begin if (reset) state = reset_pc; else case (state) // reset the computer, need to clear some registers reset_pc : begin program_counter = 8'b00000000; memory_address_register = 8'b00000000; register_A = 16'b0000000000000000; memory_write = 0; state = fetch; end // Fetch instruction from memory and add 1 to program counter fetch : begin instruction_register = memory_data_register; program_counter = program_counter + 1; memory_write = 0; state = decode; end

  15. // Decode instruction and send out address of any data operands decode : begin memory_address_register = instruction_register[7:0]; case (instruction_register[15:8]) 8'b00000000: state = execute_add; 8'b00000001: state = execute_store; 8'b00000010: state = execute_load; 8'b00000011: state = execute_jump; default: state = fetch; endcase end // Execute the ADD instruction execute_add : begin register_A = register_A + memory_data_register; memory_address_register = program_counter; state = fetch; end

  16. // Execute the STORE instruction,needs 3 clock cycles for memory write) execute_store : begin // write register_A to memory memory_write = 1; state = execute_store2; end // This state ensures that the memory address is valid until // after memory_write goes low execute_store2 : begin memory_write = 0; state = execute_store3; end execute_store3 : begin memory_address_register = program_counter; state = fetch; end

  17. // Execute the LOAD instruction execute_load : begin register_A = memory_data_register; memory_address_register = program_counter; state = fetch; end // Execute the JUMP instruction execute_jump : begin memory_address_register = instruction_register[7:0]; program_counter = instruction_register[7:0]; state = fetch; end // Default case – an undefined opcode default : begin memory_address_register = program_counter; memory_write = 0; state = fetch; end endcase end endmodule

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