Introduction

1. CSE-591 Compilers for Embedded SystemsCode transformations and compile time data management techniques for application mapping onto SIMD-style Coarse-grained Reconfigurable Architectures By,SandeepMarathe

2. Introduction • CGRAs – Performance of hardware and flexibility of software • What is Reconfigurable ? Reconfigurable functionality and data routing • SIMD architecture example • Morphosys

3. Problem Outline Objective – • To efficiently use PEs to achieve maximum parallelism possible with SIMD constraints • Reduce data/context transfers Mapping process - • Mapping of data onto Frame buffer – Data partitioning, arrangement • Mapping of operations onto PEs – map similar operations onto single Column/Row (SIMD), decision on interconnections

4. Related Work • Girish Venkataramani, Fadi Kurdahi, Wim Bohm, “A Compiler framework for Mapping Applications to a Coarse-grained Reconfigurable Architecture”, CASES 2001 • Loop Synthesis (generating a execution schedule) • Use SA-C framework (HDFG) • Element generator • Window generator • Uses SA-C programs, image processing kernels

5. Rafael Maestre et al, “A Framework for Reconfigurable Computing: Task Scheduling and Context Management”, IEEE transactions on VLSI Systems, Dec 2001 Kernel schedule – • Partition application into set of independent kernels • Scheduling within a partition Context schedule – Context selection and allocation

6. Possible Approaches To perform loop transformations so that the data access is • within the array space which can fit into the Frame buffer • Are temporally close Re-arrange data in each array space based on DFG so that PEs operate on them efficiently