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- c P u version 1.01a

NIMICA. - c P u version 1.01a. Ni zar Budhwani Mi Hai Ca sey Pollard. Introduction – 16-bit processor. Task: Build a 16-bit processor using LogicWorks 4.0 interactive circuit design tool ->. Processor Structure. Clock. Timer. Processor Structure continued….

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- c P u version 1.01a

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  1. NIMICA - c P u version 1.01a Nizar Budhwani MiHai Casey Pollard

  2. Introduction – 16-bit processor • Task: Build a 16-bit processor using LogicWorks 4.0 • interactive circuit design tool ->

  3. Processor Structure • Clock

  4. Timer

  5. Processor Structure continued…. • 12 and 16-bit registers, used for various units such as the Program Counter, Instruction Register.

  6. Arithmetic Logic Unit – to perform arithmetic functions (NOT, 2X, AND, OR, XOR and SUM)

  7. Processor Structure continued… • 16 Machine Instructions • General Purpose Register (G Register) • HLT(Machine Halt), XOR(XOR with G), AND(And with G), OR(Or with G), NOT(G) to G, LDG (Load operand to G), SDG(Send operand to G), SRJ(Subroutine Jump), JMI(Conditional Jump), JMP(Unconditional Jump), INJ (Indirect Jump), ROL(Rotate G), KTG (Keyboard to G), NOP(No operation), INT(Interrupt)

  8. CPU – So what does it look like?Exhibit One

  9. Problems encountered • The signal will get weak in the transmission; for example, a strange problem we have encountered during the design. We got a signal 1 at the left side of bus, but it dropped to 0 at the right side. We kept asking why until we found that if we use a buffer, the problem was gone. So, we made a conclusion that the signal will get weak in the transmission. The solution is to use a buffer to boost up the signal. • We made a special timer without using boosters. It works fine. • Every instruction added would change the timing, so delays were added after each instruction to make the timing work perfectly (very frustrating)

  10. Exhibit 2 • Logic Works 4.0 Demo

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