Development System using Altium Designer

1. Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Development System using Altium Designer Midterm Presentation One Semester Project “Spring 2007” Supervisor : Ina Rivkin Performed by: Fared Ghanayim Jihad Zahdeh

2. Agenda • Project Goals. • Design block Diagram. • Schematic building • Schedule

3. Project Goals • Building a design using Altium Designer • Knowing different features of Altium Designer • Building the Schematic Diagram • Using VHDL for implementing one of the schematic units and Simulation and Synthesis. • Embedded code. • Signal Integrity.

4. Design Block Diagram

5. Schematic Building Creating a new FPGA Project

6. Major units we used in schematics and their Libraries

7. Top Level Design Timing LCD Controller LCD SRAM Processor Memory Controller JTAG

8. SRAM Description OF SRAM PINS: Data I/O Enable Address Write Enable Output Enable Upper Bit Lower Bit

9. Top Level Design Diagram FPGA Microprocessor Block

10. CPU Diagram with internal Mem. Microprocessor Clock and Reset ports ROM Input Output Ports

11. Top Level Design Diagram Memory Controller Block

12. Memory Controller Implementation in VHDL libraryIEEE; useIEEE.Std_Logic_1164.all; entity Mem_cont isport ( sel : instd_logic; inp : instd_logic_vector(15 downto 0); outp : outstd_logic_vector(15 downto 0); io : inoutstd_logic_vector(15 downto 0); IMEM : instd_logic_vector(7 downto 0); IADDR : instd_logic_vector(15 downto 0); OADDR : outstd_logic_vector(18 downto 0); OCS : outstd_logic; OUB : outstd_logic; OLB : outstd_logic ); end Mem_cont; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- architecture strc of Mem_cont is begin outp <= io when sel = '0' else (others=>'Z'); io <= inp when sel = '1' else (others=>'Z'); OADDR(0) <= IADDR(0); OADDR(1) <= IADDR(1); OADDR(2) <= IADDR(2); OADDR(3) <= IADDR(3); OADDR(4) <= IADDR(4); OADDR(5) <= IADDR(5); OADDR(6) <= IADDR(6); OADDR(7) <= IADDR(7); OADDR(8) <= IADDR(8); OADDR(9) <= IADDR(9); OADDR(10) <= IADDR(10); OADDR(11) <= IADDR(11); OADDR(12) <= IADDR(12); OADDR(13) <= IADDR(13); OADDR(14) <= IADDR(14); OADDR(15) <= IADDR(15); OLB <= IMEM(0); OUB <= not IMEM(0); OCS <= '1'; OADDR(16) <= IMEM(1); OADDR(17) <= IMEM(2); OADDR(18) <= IMEM(3); end strc ;

13. Schedule • 14/6 Presenting midterm Presentation. • 15/6 – 29/6 Embedded code and compilation • 30/6 – 7/7 simulation and synthesis . • 8/7 – 15/7 Signal Integrity. • 1/8 Final Presentation.