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Simulação para vários instrusões VHDL

Simulação para vários instrusões VHDL. 1. Funções;. entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0)); end VHDL_test;. for i in input'range loop temp := temp xor input(i); end loop;.

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Simulação para vários instrusões VHDL

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  1. Simulação para vários instrusões VHDL

  2. 1. Funções;

  3. entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0)); end VHDL_test; for i in input'range loop temp := temp xor input(i); end loop; para o nosso exemplo i vai ser alterado de 7 a 0 chamada da função function function_name (parameter_list) return type is < declarations> begin <sequential statements> end function_name architecture Behavioral of VHDL_test is function parity (input : std_logic_vector) return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; begin data_out <= "000" & parity(data_in); end Behavioral; Esta função é válida para qualquer tamanho de entrada (parâmetro - input ) Example in VHDL_AF.zip

  4. Exemplo 1 entity Function_test is generic (size : natural := 8); Port( data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic); end Function_test; architecture Behavioral of Function_test is function parity (input : std_logic_vector) return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; begin data_out <= parity(data_in); end Behavioral;

  5. Exemplo 2 entity Function_countOne is generic (size : natural := 8); Port( data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic_vector(3 downto 0); data_out_int : out integer range 0 to 8); end Function_countOne; architecture Behavioral of Function_countOne is function count_one (input : std_logic_vector) return integer is variable temp : integer range 0 to 8 := 0; begin for i in input'range loop if input(i) = '1' then temp := temp+1; end if; end loop; return temp; end count_one; begin data_out <= std_logic_vector(to_unsigned(count_one(data_in),4)); data_out_int <= count_one(data_in); end Behavioral;

  6. Exemplo 3 entity Function_countOneClk is generic (size : natural := 8); Port( clk : std_logic; data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic_vector(3 downto 0); data_out_int : out integer range 0 to 8); end Function_countOneClk; architecture Behavioral of Function_countOneClk is function count_one (input : std_logic_vector) return integer is variable temp : integer range 0 to 8 := 0; begin for i in input'range loop if input(i) = '1' then temp := temp+1; end if; end loop; return temp; end count_one; begin process (clk) begin if rising_edge(clk) then data_out <= std_logic_vector(to_unsigned(count_one(data_in),4)); data_out_int <= count_one(data_in); end if; end process; end Behavioral;

  7. 2. Procedimentos;

  8. procedureprocedure_name (parameter_list) is declarations begin sequential_statements endprocedure_name architecture bhv of lcd is -- . . . . . . . . . . . . . . . . . . . . . proceduredec4_bcd (signal dec4 : in std_logic_vector(3 downto 0); signal bcdM : out std_logic_vector(3 downto 0); signal bcdL : out std_logic_vector(3 downto 0)) is begin case dec4 is when "0---" | "100-" => bcdM <= (others=>'0'); bcdL <= dec4; when others => bcdM <= "0001"; bcdL <= dec4 + "0110"; end case; enddec4_bcd; -- . . . . . . . . . . . . . . . . . . . . . begin -- . . . . . . . . . . . . . . . . . . . . . Este procedimento converte um valor binário de 4 bits para um valor BCD de 8 bits, onde bcdL é o dígito menos significativo e bcdM é o dígito mais significativo

  9. Exemplo entity Procedute_test is generic (size : natural := 4); Port( data_in : in std_logic_vector(size-1 downto 0); data_outMS : out std_logic_vector(size-1 downto 0); data_outLS : out std_logic_vector(size-1 downto 0) ); end Procedute_test; architecture bhv of Procedute_test is procedure dec4_bcd (signal dec4 : in std_logic_vector(3 downto 0); signal bcdM : out std_logic_vector(3 downto 0); signal bcdL : out std_logic_vector(3 downto 0)) is begin case conv_integer(dec4) is when 0 to 9 => bcdM <= (others=>'0'); bcdL <= dec4; when others => bcdM <= "0001"; bcdL <= dec4 + "0110"; end case; end dec4_bcd; begin dec4_bcd(data_in,data_outMS,data_outLS); end bhv;

  10. 3. Generate

  11. REG clk rst estado corrente (CS) next state (NS) D Flip-Flop with Asynchronous Clear da biblioteca do Xilinx label: for parameter in range generate concurrent statements end generatelabel; A construção for … generate pode ser usada para criar um array de componentes, por exemplo: generic ( R : integer := 3; -- outros generic statements ); -- . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_reg: -- registo de MEF for i in 0 to R-1 generate REG: FDC port map (CS(i),clk,rst,NS(i)); end generate FSM_reg;

  12. Exemplo entity Flip_flop is Port( clk : in std_logic; rst : in std_logic; bit_in : in std_logic; bit_out : out std_logic); end Flip_flop; architecture MyFF of Flip_flop is begin process(rst,clk) begin if rst ='1' then bit_out <= '0'; elsif rising_edge(clk) then bit_out <= bit_in; end if; end process; end MyFF;

  13. entity Generate_test is generic (size : natural := 8); Port( clk : in std_logic; rst : in std_logic; data_in : in std_logic_vector(size-1 downto 0); data_out : out std_logic_vector(size-1 downto 0)); end Generate_test; architecture MyArch of Generate_test is component Flip_flop is Port( clk : in std_logic; rst : in std_logic; bit_in : in std_logic; bit_out : out std_logic); end component; begin FSM_reg: -- registo for i in 0 to size-1 generate REG: Flip_flop port map (clk,rst,data_in(i),data_out(i)); end generate FSM_reg; end MyArch;

  14. 3. Arrays

  15. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; package empty is type columns is range 1 to 4; type row is array (columns) of std_logic; end empty; package body empty is --begin end empty; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL;

  16. use work.empty.all; entity Test_arrays is Port( Myr1,Myr2,Myr3,Myr4,Myr5 : out row ); end Test_arrays; Architecture Beh of Test_arrays is type columns is range 1 to 4; type row is array (columns) of std_logic; signal r1 : work.empty.row := ('1', '0', '1', '1'); signal r2 : work.empty.row := (1 => '1', 2 => '0', others => '1'); signal r3 : work.empty.row := (1 => '1', 2 => '0', 3 to 4 => '1'); signal r4 : work.empty.row := (2 => '0', others => '1'); signal r5 : work.empty.row := (1 | 3 | 4 => '1', 2 => '0'); begin Myr1 <= r1; Myr2 <= r2; Myr3 <= r3; Myr4 <= r4; Myr5 <= r5; end Beh;

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