Supply Voltage Noise Aware ATPG for Transition Delay Faults

1. Supply Voltage Noise Aware ATPG for Transition Delay Faults Nisar Ahmed and M. Tehranipoor University of Connecticut Vinay Jayaram Texas Instruments, TX

2. Overview • Objective • Prior Work • Statistical IR-drop Analysis • Power Model • Switching Cycle Average Power (SCAP) • SCAP Calculator • Pattern Generation Framework • Experimental Results • Conclusions

3. How to generate IR-drop tolerant patterns without significantly increasing number of patterns? Objective • High switching activity during test compared to functional operation • Increased sensitivity of VDSM designs to supply noise • IR-drop during at-speed test: A BIG CONCERN • Present ATPG tools are supply noise unaware • Targets as many faults as possible per pattern • Random filling of X’s during ATPG • Increases switching activity of test patterns

4. IR-drop Effects? • Delay Failure • An excessive IR-drop can increase the delay of targeted paths • Logic Failure • An excessive IR-drop can significantly reduce the voltage reaching a device -- may function unpredictably • Question: • What is the impact of IR-drop on long and short paths • Answer: • Slack of a path and number of switching define how tolerant a path is to IR-drop

5. Prior Work • IR-drop issue during at-speed test [Saxena, ITC03] • Static Verification of Test Vectors for IR-drop Failure [Kokrady, ICCAD03] • Power Supply Noise Analysis in Test Compaction [Wang, ITC05] • Preferred-Fill [Remersaro, IEEE D&T 07] • Low-capture TDF pattern generation [Wen, VTS05, VTS06] • Faster-than-at-speed test considering IR-drop [Ahmed, ICCAD03]

6. Contributions • Novel Power model to measure the average power during at-speed test • Called Switching cycle average power (SCAP) • Consider both the length of paths affected by each pattern and the number of transitions • Pattern generation procedure: • Set SCAP threshold • Perform TDF pattern generation • Identify high IR-drop patterns using SCAP • Replace them with IR-drop patterns

7. Case Study • ITC’99 benchmark (b19) • 200K gates, 6642 scan cells • 8 scan chains • 4 VDD (VSS) pads • 0.18 nm technology • Frequency = 142MHz • Power rings Width = 20um • Stripes Width = 10um Power/Ground Distribution Network

8. Statistical IR-drop analysis • Vector-less approach to estimate IR-drop analysis • Assumptions: • Uniform activity over the entire design region • Switching time frame = clock period • 20% Net toggle activity • 2.8% voltage drop in VDD network • 4.5% voltage drop in VSS network • Underestimates average functional IR-drop and power • Non-uniform switching activity • Most activity occurs during early cycle period IR-drop inversely proportional to switching time-frame window

9. Statistical IR-drop analysis (cont.) What is an average switching time-frame window to estimate average functional IR-drop and power ? • Procedure: • Generate transition fault test patterns • Measure time-span of all switching activity during launch-to-capture window • Average switching time frame = Half cycle period Functional power threshold to identify high IR-drop test patterns

10. Clock Network Switching ATE clock T FF clock STW (P2) Scan Enable STW (P1) Power Model (SCAP) • Average IR-drop directly relates to average power • Cycle average power (CAP) • Power measured over entire cycle period • Switching cycle average power model (SCAP) • Measured over switching time frame window (STW) CAP = ∑(Ci * VDD2)T SCAP = ∑(Ci * VDD2)STW

11. Power Model (SCAP) (cont.) • Pattern P1 and P2 • Almost same switching activity • Different switching time frame window (STW) • P2 has smaller STW • SCAP(P2)> SCAP(P1) IR-drop effects on VDD and VSS during pattern P1 and P2 application within 7ns capture window.

12. Power Model (SCAP) (cont.) • SCAP(P2)> SCAP(P1) ITC’99 benchmark (b19) P2 P1 Switching time frame window (STW) is an important parameter

13. SCAP Model Validation Another example: Cadence SOC Design (Turbo Eagle) P2 P1 SCAP is a good power model to represent average IR-drop

14. Test Patterns Design (.v) Physical Design (DEF) SDF SCAP Calculator STAR-RXCT PLI VCS Pattern Power Profile Instance Capacitance extractor Parasitics (SPEF) SCAP Calculator • PLI routine to measure power during launch-to-capture window • Avoids huge VCD file generation for large designs • SCAP = ∑(Ci * VDD)2 STW SDF – Standard delay format (Timing Information) VCS – Gate level simulator (Synopsys) PLI – Programmable language Interface STAR-RXCT – Extraction tool (Synopsys)

15. Commercial ATPG tool FS ATPG Statistical IR-drop Analysis Fault List Pattern Set SCAP Calculator Thr Yes If SCAP>Thr ? Short-listed Patterns No Exit Pattern Generation Framework With X-fill options Pattern Generation Procedure: Step 1: Run ATPG for all faults Step 2: Exclude high IR-drop Patterns (short-listed patterns) Step 3: Fault Simulate for Short-listed patterns  fault list Step 4: Run ATPG for this fault list

16. Experimental Results SCAP threshold = 20% toggle activity over avg. switching time frame window • Conventional transition fault pattern set • Random fill option for don’t-care bits • 2360 patterns generated VSS network VDD network 860 patterns with SCAP value above threshold

17. Results (cont.) • New patterns generated with fill-0 and fill-1 options for faults exclusively detected by short-listed patterns • Fill-0 generates 957 low-power patterns instead of 860 patterns with high SCAP value • 97 extra patterns but significantly reduces the SCAP value Fill-0 option

18. Results (cont.) Fill-1 option Fill Adjacent

19. Results (cont.) • Comparison of conventional ATPG and the new pattern generation procedure • Slight increase in pattern volume • 4% increase in number of patterns

20. Conclusion • New pattern generation procedure for IR-drop tolerant pattern generation • Switching cycle average power (SCAP) model for identifying high IR-drop patterns • Considers both switching capacitance and time frame of activity • PLI based SCAP calculator • Efficient way to measure SCAP during launch-to-capture window