1 / 20

Michel Vasilevski Hassan Aboushady, Marie-Minerve Louërat

Automatic Model Refinement of GmC Integrators for High-Level Simulations of Continuous-Time Sigma-Delta Modulators. Michel Vasilevski Hassan Aboushady, Marie-Minerve Louërat. Laboratory LIP6 University Pierre and Marie Curie, Paris 6, France. May 2009. Outline. Motivations

marci
Download Presentation

Michel Vasilevski Hassan Aboushady, Marie-Minerve Louërat

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Automatic Model Refinement of GmC Integrators for High-Level Simulations of Continuous-Time Sigma-Delta Modulators Michel Vasilevski Hassan Aboushady, Marie-Minerve Louërat Laboratory LIP6 University Pierre and Marie Curie, Paris 6, France May 2009

  2. Outline • Motivations • GmC Model Refinement • Characterization Flow • Results and Application • Conclusion Laboratory LIP6, University Paris6

  3. Outline • Motivations • GmC Model Refinement • Characterization Flow • Results and Application • Conclusion Laboratory LIP6, University Paris6

  4. Motivations : Analog Design Flow System-Level Simulation Modify Parameters Performance analysis OK Sizing : Manual Model Refinement Simulation Modify Parameters Performance analysis System-Level Specifications Circuit-Level Specifications Circuit Topology Sized Netlist Circuit-Level Circuit OK Laboratory LIP6, University Paris6

  5. Continuous-Time SD Modulator 1/T + + - - DAC With Accurate Integrators Model With Ideal Integrators Model Laboratory LIP6, University Paris6

  6. Outline • Motivations • GmC Model Refinement • Characterization Flow • Results and Application • Conclusion Laboratory LIP6, University Paris6

  7. GmC Model Refinement GmC ideal Transfer Function: Laboratory LIP6, University Paris6

  8. GmC Non-Idealities CMOS Process: 0.13 μm Laboratory LIP6, University Paris6

  9. Simplified GmC Model [Zele,Allstot,JSSC’96] Simplified models are not sufficiently accurate Laboratory LIP6, University Paris6

  10. Accurate Cascoded GmC Model Laboratory LIP6, University Paris6

  11. Outline • Motivations • GmC Model Refinement • Characterization Flow • Results and Application • Conclusion Laboratory LIP6, University Paris6

  12. Characterization Flow : Conventional method System-Level Simulation Modify Aint, OSR SNR analysis scaling OK Circuit-Level System-Level Specifications : SNR, BW GmC Model GmC Specifications GmC Topology Sizing : Manual Zeros/Poles Extraction Sized Netlist Simulation Modify Parameters Circuit OK Performance analysis Laboratory LIP6, University Paris6

  13. Characterization Flow : Full Automation • SystemC-AMS • C++ based tool. • Fixed step discrete-time System-Level simulator. • Adapted to mixed analog-digital systems modeling. • Ongoing standardization (extension SystemC). • CAIRO+: • C++ based tool. • Exact Bsim3v3 models are used for transistor sizing. • Small-Signal parameters extraction. • Suited for technology migration. • Fullinteroperability. Laboratory LIP6, University Paris6

  14. Characterization Flow : Proposed Method SystemC-AMS SystemC-AMS GmC Model Simulation Modify Aint, OSR SNR analysis scaling OK C++ GmC Specifications GmC Topology Sizing : Synthesis CAIRO+ CAIRO+ Sized Netlist Small-Signal Parameters System-Level Specifications : SNR, BW Zeros/Poles Symbolic expression Laboratory LIP6, University Paris6

  15. Characterization Flow : Full Automation Laboratory LIP6, University Paris6

  16. Outline • Motivations • GmC Model Refinement • Characterization Flow • Results and Application • Conclusion Laboratory LIP6, University Paris6

  17. 2nd order CT SD in a 0.13 mm CMOS Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz GmC Frequency Response SD output Power Spectral Density SNR=47dB SNR=68dB Transistors length: L1=10μm, L3=9 μm Laboratory LIP6, University Paris6

  18. 2nd order CT SD in a 0.13 mm CMOS Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz GmC Frequency Response SD output Power Spectral Density SNR=68dB SNR=68dB Transistors length: L1=3 μm, L3=0.18 μm Laboratory LIP6, University Paris6

  19. Technology migration : 0.25 μm / 0.13 μm Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz/10MHz SNR=52dB SNR~68dB Laboratory LIP6, University Paris6

  20. 5 - Conclusion • Automatic refinement of high-level system models based on: • Exact symbolic expressions for small signal analysis • Accurate BSIM3v3 transistor models • Homogeneous Environment (C++): • High-Level Simulation => SystemC-AMS • Circuit synthesis and characterization => CAIRO+ • Proposed method illustrated on the GmC integrator of a 2nd order SD modulator. Laboratory LIP6, University Paris6

More Related