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Class Exercise 1A

This class exercise focuses on logic gates and encoders in FPGA and ASIC design using VHDL. Students will be asked to recall different types of gates, define logic functions, identify minimum gate sets, express logic functions, understand De Morgan's Laws, implement decoders, differentiate between encoders and priority encoders, and implement adders.

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Class Exercise 1A

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  1. Class Exercise 1A

  2. Rules • If you believe that you know a correct answer, please raise your hand • I will select one or more students (independently whether an answer given by the first student is correct or incorrect) • Please, identify yourself by first name and give an answer • Correct answer = 1 bonus point ECE 448 – FPGA and ASIC Design with VHDL

  3. Problem 1 List all 2-input logic gates that you can recall.

  4. Problem 2 How many 2-input logic functions can be theoretically defined (whether they make sense or not)?

  5. Problem 3 List all 1-input logic gates.

  6. Problem 4 What is a minimum set of gates that can be used to implement all logic functions?

  7. Problem 5 List four ways of expressing logic functions.

  8. Problem 6 What are the De Morgan’s Laws? Write their equations and draw their schematic representation.

  9. Problem 7 How many select inputs does an 8-to-1 MUX have? How many select inputs does an n-to-1 MUX have?

  10. Problem 7 How many outputs does a decoder with two data inputs have? How many outputs does a decoder with n data inputs have?

  11. Problem 8 Show how to implement a decoder that recognizes the following 4 ranges of a 16-bit address A, and generates the corresponding enable signals e0,e1,e2,e3: For A in: Assert C000-CFFF: e0 D000-DFFF: e1 E000-EFFF: e2 F000-FFFF: e3

  12. Problem 9 How many inputs does an encoder with two data outputs have? How many inputs does an encoder with n data outputs have?

  13. Problem 10 What is a difference between encoder and priority encoder?

  14. Problem 11 Show how to implement Priority Encoder using multiplexers and a minimum number of logic gates

  15. Problem 12 What is a difference between an adder, half-adder, and full-adder?

  16. Problem 13 Show how to implement Full Adder using 8-to-1 multiplexers only

  17. Problem 14 Show how to implement Full Adder using 4-to-1 multiplexers and inverters only

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