Conversion Driven Design of Binary to Mixed Radix Circuits

1. Conversion Driven Designof Binary to Mixed Radix Circuits Ashur Rafiev, Julian Murphy, Danil Sokolov, Alex Yakovlev School of EECE, Newcastle University, UK {ashur.rafiev, j.p.murphy, danil.sokolov, alex.yakovlev}@ncl.ac.uk ICCD 2008

2. Outline • Switching Balanced Codes • Conversion Driven Design (CDD) • Motivation • Conversion Basics • Bitwise Approach • Bitwise Gate Grouping Algorithm • Artificial Combinational Loops Problem • Operandwise Approach • Operandwise Gate Grouping Algorithm • Benchmark Results • Conclusions Outline ICCD 2008

3. Switching Balanced Codes M-of-N data encoding: data signal is represented with • N wires • M of them are active (high) Return-to-zero (RTZ) protocol: data signals are separated with dummy signals (spacers) Application areas: • Security • Asynchronous system design • Network-on-chip communication Switching Balanced Codes ICCD 2008

4. 1-of-2 (Dual-Rail) and 1-of-4 Encodings ICCD 2008

5. Outline • Switching Balanced Codes • Conversion Driven Design • Motivation • Conversion Basics • Bitwise Approach • Bitwise Gate Grouping Algorithm • Artificial Combinational Loops Problem • Operandwise Approach • Operandwise Gate Grouping Algorithm • Benchmark Results • Conclusions Outline ICCD 2008

6. + Higher radix signals consume less power and reduce cross-talk effect – Require multi-valued logic synthesis + Some tools and techniques already exist (e.g. MV-SIS) – Moving away from the RTL design flow is frequently frowned upon by industry Reuse existing popular design tools for multi-valued system design Conversion Driven Design: Motivation ICCD 2008

7. EDA Tool Synthesize binary circuit from specification • Conversion Tool • fast • fully automated HDL specification Flatten components to the gate level netlist Component library Place and route AREA OF THE RESEARCH Final design Conversion Driven Design Flow Convert to mixed radix component level design ICCD 2008

8. quaternary inputs quaternary outputs quaternary … … mixers splitters binary inputs binary outputs binary … … … … Conversion Basics Original binary datapath is given as a structural HDL netlist. Pairs of binary signals can be grouped into quaternary. Certain part of the circuit may remain binary. ICCD 2008

9. Conversion Basics Signal converters: • A splitter converts one quaternary signal into two binary. • A mixer converts two binary signals into one quaternary. • The way the signals (gates) are grouped determines the efficiency of the conversion, therefore the conversion problem corresponds directly to the gate grouping problem. ICCD 2008

10. Outline • Switching Balanced Codes • Conversion Driven Design • Motivation • Conversion Basics • Bitwise Approach • Bitwise Gate Grouping Algorithm • Artificial Combinational Loops Problem • Operandwise Approach • Operandwise Gate Grouping Algorithm • Benchmark Results • Conclusions Outline ICCD 2008

11. 4 4 4 A0A1 Q0Q1 B0B1 Bitwise Gate Grouping A={A0, A1} B={B0, B1} Q = {Q0, Q1} Q = A·B Q0 = A0·B0 Q1 = A1·B1 a bitwise quaternary component ICCD 2008

12. Bitwise Gate Grouping Algorithm • Uses heuristics to extract bitwise meaning of signals from the flat netlist. • Input and output port grouping is given • Algorithm is iterative, based on breadth-first search • Bitwise Regularity Ratio is used as an estimation criteria. It is calculated for each gate pair on each iteration. Bitwise Regularity Ratio (BRR) depends on how many quaternary links a pair of gates can form with respect to the state of the conversion on the given iteration. ICCD 2008

13. BRR=2 BRR=2 BRR=2 BRR=2 BRR=1 BRR=2 BRR=1 BRR=1 Bitwise Gate Grouping Algorithm: Example original circuit converted circuit * mixed radix components are shown as black boxes ICCD 2008

14. Artificial Combinational Loops • Combinational loops can appear during the bitwise conversion while the original circuit is free of combinational loops. • Need special methodology to handle. Problems: • If mixers wait for valid data from both inputs – deadlock. • If mixers produce output regardless to spacers – invalid output. • A signal should pass artificial combinational loop exactly 2 times before it produce a valid output. ICCD 2008

15. Bitwise Gate Grouping Disadvantages of the algorithm: • Computational cost O(N) = 2N2log22N, N is a number of gates in the original circuit. Disadvantages of the approach: • Inefficient for circuits without bitwise nature of signals, e.g.S-boxes. • The algorithm can produce combinational loops. Bitwise (naive) approach is inefficient for CDD. ICCD 2008

16. Outline • Switching Balanced Codes • Conversion Driven Design • Motivation • Conversion Basics • Bitwise Approach • Bitwise Gate Grouping Algorithm • Artificial Combinational Loops Problem • Operandwise Approach • Operandwise Gate Grouping Algorithm • Benchmark Results • Conclusions Outline ICCD 2008

17. A0 4 4 4 4 4 4 Q0 A0B0 A0A1 B0 Q0Q1 Q0Q1 A1 Q1 A1B1 B0B1 B1 Operandwise Gate Grouping • Bitwise grouping is derived from the functional meaning of signals. • Operandwise grouping is derived from the structural positioning of gates – works with 2-input gates only. a bitwise quaternary component an operandwise quaternary component ICCD 2008

18. Binary Trees Approach For binary tree structures within a netlist we can group inputs and outputs of gates to perform an operandwise grouping. ICCD 2008

19. Binary Trees Approach Signals cannot be shared between groups, because it leads to duplication of gates. Gates with multiple fanout block operandwise grouping. – Remain binary ICCD 2008

20. Quaternary-to-Binary Gates (Q/B Gates) Q/B gate – a gate with one quaternary input and one binary output. ICCD 2008

21. Quaternary-to-Binary Gates (Q/B Gates) • A Q/B gate is a mixed radix component. • A Q/B gate is an incomplete operandwise group. • It can replace a splitter followed by a binary gate. ICCD 2008

22. Operandwise Gate Grouping Algorithm • Phase I: group all signals regardless of gate fanouts (some gates will be duplicated). • Output ports can be grouped arbitrarily. • Phase II: analyse duplicates and discard groups leading to duplication. • Phase III: insert signal converters and Q/B gates. Computational cost of the algorithm is O(N) = 3N, where N is a number of gates in the original circuit. ICCD 2008

23. Operandwise Gate Grouping Algorithm: Example original circuit converted circuit Phase I Phase II Phase III ICCD 2008

24. Operandwise Gate Grouping Advantages of the algorithm: • Low computational cost. • It is highly modular: one can add more passes to the algorithm to increase efficiency of the conversion. Disadvantages of the algorithm: • Can produce significant “fractioning” of binary and quaternary parts of the circuit increasing the number of signal converters required. ICCD 2008

25. Benchmark Results * original single-rail circuits were optimised in Synopsys. ICCD 2008

26. Outline • Switching Balanced Codes • Conversion Driven Design • Motivation • Conversion Basics • Bitwise Approach • Bitwise Gate Grouping Algorithm • Artificial Combinational Loops Problem • Operandwise Approach • Operandwise Gate Grouping Algorithm • Benchmark Results • Conclusions Outline ICCD 2008

27. Conclusions • Conversion driven design technique was suggested in order to reuse popular EDA tools for MVL synthesis. • Binary and quaternary mixed radix was selected to improve the efficiency of the conversion. • Two conversion (gate grouping) algorithms were implemented and analysed. • Bitwise approach is not efficient for CDD • Operandwise approach is fast and flexible but not efficient enough in terms of saving switching energy. Future work: • Improve operandwise component implementations. • Add more heuristics to the operandwise algorithm to increase the efficiency of the conversion. ICCD 2008

28. The End Thank you! Questions? ICCD 2008