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PROCESSOR ARCHITECTURE

PROCESSOR ARCHITECTURE. Jehan-François Pâris jparis@uh.edu. Chapter Organization. Logic design conventions Implementation of a "toy" CPU Pipelining Pipelining hazards Data hazards Control hazards Exceptions Parallelism. IMPORTANT. LOGIC DESIGN CONVENTIONS.

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PROCESSOR ARCHITECTURE

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  1. PROCESSOR ARCHITECTURE Jehan-François Pâris jparis@uh.edu

  2. Chapter Organization • Logic design conventions • Implementation of a "toy" CPU • Pipelining • Pipelining hazards • Data hazards • Control hazards • Exceptions • Parallelism IMPORTANT

  3. LOGIC DESIGN CONVENTIONS

  4. Combinational/state elements • Combinational elements: • Outputs only depend on current inputs • Stateless • Adders and, more generally, arithmetic logic unit (ALU)

  5. Combinational/state elements • State elements: • Have a memory holding a state • Output depends on current inputs and state of element • State reflects past inputs • Flip-flops, …

  6. Judicial analogy • In our legal system • Guilty/not guilty decision is stateless • Good reasons • Sentencing decision is not • "Three strikes and you are out" laws • Good reasons

  7. Clocking methodology • We will assume an edge-triggered clocking technology • Edge is short-enough to prevent data propagation in state elements • Can read current state of a memory element at the same time we update it

  8. Clocking convention • Omit write control signal if state element is updated at every active clock edge

  9. A "TOY" CPU

  10. Motivation • "Toy" CPU will implement a subset of MIPS instruction set • Subset will be • Self-sufficient • Simpler to implement • Complex enough to allow a serious discussion of CPU architecture

  11. The subset • Will include • Load and store instructions:lw (load word) and sw (store word) • Arithmetic-logic instructions:add, sub, and, or and slt (set less than) • Branch instructions:beq (branch if equal) and j (jump)

  12. Load and store instructions • Format I • Three operands: • Two registers $r1 and $r2 • One displacement d • lw $r1, d($r2) loads into register $r1 main memory word at address contents($r2) + d • sw $r1, d($r2) stores contents of register $r1 into main memory word at address contents($r2) + d

  13. Arithmetic-logic instructions • Format R • Three operands: • Three registers $r1, $r2 and $r3 • Store into register $r1 result of $r2 <op> $r3where <op> can be add, subtract, and, oras well as set if less than

  14. Branch instruction • Format I • Three operands: • Two registers $r1 and $r2 • One displacement d • beq $r1, $r2, dset value of PC to PC+4 + 4×diff $r1 = $r2

  15. The simplest data path • Assume CPU will do nothing but • Incrementing its program counter and • Deliver the next instruction

  16. The simplest data path Add 4 InstructionMemory Read address Instruction PC

  17. Implementing R2R instructions • Takes two 32-bit inputs • Returns • A 32-bit output • A 1-bit signal if the result is zero

  18. The register file • Two read outputs that are always available • One write input activated by a RegWrite signal • Three register selectors

  19. 5 5 The register file Read select 1 Read data 1 Read select 2 Read data 2 Write select Write data 5 RegWrite:enables register writes

  20. Implementing R2R instructions Registerfile ALU Result RegWrite is enabled

  21. Implementing load and store • Require • An address calculation: • contents($r2) + d • An access to data memory • Before doing the address calculation, we must transform 16-bit displacement d into a 32-bit value using sign extension

  22. The data memory • One address selector • One write data input • One read data output • Two controls • MemWrite • MemRead

  23. 0000 0000 0000 0000 0110 1010 1010 0100 Sign extension (I) • If 16-bit number has a zero as MSB • It is positive • Must add 16 zero bits 0110 1010 1010 0100

  24. 1111 1111 1111 1111 1110 1010 1010 0100 Sign extension (II) • If 16-bit number has a one as MSB • It is negative • Must add 16 one bits 1110 1010 1010 0100

  25. The data memory MemWrite: enables memory writes Memory address Read data Write data MemRead: enables memory reads

  26. Implementing the store instruction Registerfile ALU Address Read Write SE Sign-extended d field

  27. Implementing the load instruction Registerfile ALU Address Read Write SEd field SE

  28. Implementing conditional branch • Target Address: • Sign-extend 16-bit immediate part of instruction • Shift left 2 • Add to PC • Branch Control Logic: • Perform test operation on two registers • Check result

  29. SE Implementing conditional branch Branch Destination PC+4 Add Shiftleft 2 Registerfile To branch control logic ALU d field of instruction Sign-extended d field

  30. Note • Arithmetic-logic operations only use • Register file and ALU • Load and store use • ALU for computing memory address • Data memory

  31. Implementing other instructions

  32. Combining everything

  33. Left to be done • All control signals: • Two multiplexers: ALUSrc and MemtoReg • RegWrite, MemRad and MemWrite switches • ALU controls (4 bits)

  34. ALU control signals

  35. Controlling the ALU • Recall that all R-format instructions have same opcode • Operation performed by ALU is specified in the function field (bits <0:5>)

  36. Controlling the ALU • ALU control inputs generated by two-step process • Construct two ALUOp control bits fromopcode • Construct four ALU control bits using • Two ALUop bits • Six bits from function fieldwhen they are needed

  37. Dependence table

  38. Notes • Two step process simplifies combinatorial logic • Many don't care conditions in truth table

  39. Truth table

  40. Note • Bits 4 and 5 of function field are not used • ALUOp bits only have three possible values:00, 01 and 10 • Introduces don't care conditions • All R instructions use same data paths • Other control bits depend only on opcode

  41. Control signal effects

  42. Control signal effects

  43. Note • PCSrc is asserted when • Instruction is a branch and • ALU Zero result bit is asserted • We will introduce a Branch control line

  44. Control line settings

  45. Control line settings

  46. Active datapaths for a R instruction

  47. Active datapaths for a load instruction

  48. Active datapaths for a beq instruction

  49. The “weird" jump instruction • Uses J format • Single 26 bit operand • Implements an unconditional jump • New value of PC is obtained as follows • Bits 1:0 are zero (address is multiple of 4) • Bits 28:2 come from jump operand • Bits 31:29 come from PC+4

  50. Implementing the jump instruction

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