Algorithm & Tools for Test & Diagnosis

1. Algorithm & Tools forTest & Diagnosis Sybille Hellebrand,Viktor Fröse,Rüdiger Ibers,Marc Hunger,Michael Schnittger

2. Algorithm & Tools for Test & Diagnosis • Major challenges: • Increasing complexity of IC • Heterogeneity of systems • Impact of parameter variations • Course • Block "Microelectronics“ in Electrical Engineering and Computer Engineering (Master program or main study period for Diploma) • 30 min oral presentation and paper (IEEE format, 6 pages)

3. Overview • ATPG • Fault-models & BIST for interconnections • Test response Compaction • Statistical timing analysis

4. ATPG Test pattern generation for (very) large circuits needs efficient algorithms Different algoithms have been introduced: Structure oriented SAT based Implication graph

5. ATPG Schulz, Trischler, Sarfert, “SOCRATES: A Highly Efficient Automatic Test Pattern Generation System,” IEEE Trans. on CAD, Vol. 7, No. 1, pp. 126-137, Jan. 1988 Tafertshofer, Ganz, Henftling, “A SAT-Based Implication Engine,” Technischer Bericht, TU-München, 22. April 1997 Gizdarski, Fujiwara, “SPIRIT: A Highly Robust Combinational Test Generation Algorithm,” IEEE Trans. on CAD, Vol. 21, No. 12, pp. 1446-1458, Dec. 2002

6. Overview • ATPG • Fault-models & BIST for interconnections • Test response compaction • Statistical timing analysis

7. Motivation • Shrinking feature size • Aging effects • Electron/thermal migration • Dielectric breakdown • Interconnect driver parameter variation Faulty interconnects

8. Your Tasks • Explain faults for interconnects and their impact to the signal integrity • Bridging/resistive bridging, stuck-at / stuck-open, crosstalk • Describe the corresponding fault models • Give a short overview to a built-in self-test mechanisms

9. Literature • Cuviello, Dey, Bai, and Zhao, ”Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects,”International Conference on Computer Aided Design, 1999, pp. 297 - 303 • Grecu, Pande, Ivanov, and Saleh,“BIST for Network-on-Chip Interconnect Infrastructures,“Proceedings 24th IEEEVLSI Test Symposium, 2006

10. Overview • ATPG • Fault-models & BIST for interconnections • Test response compaction • Statistical timing analysis

11. Problem • Signature sufficient for pass/fail classification of chips • Multiple Input Signature Register (MISR) widely used • But floating buses and uninitialized memory result in X-values in signature

12. Dealing with X-Values • X-masking • X-canceling • Compaction based on convolutional codes

13. X-Masking • Mask unknown values before MISR • But: specific masking → high data overhead overmasking → possible error coverage loss J. Rajski; J. Tyszer; G. Mrugalski; W.-T. Cheng; N. Mukherjee; M. Kassab, "X-Press Compactor for 1000x Reduction of Test Data," Test Conference, 2006. ITC '06. IEEE International , vol., no., pp.1-10, Oct. 2006

14. X-Canceling • X’s effect multiple MISR outputs • XORing outputs can cancel X-values • X-canceled MISR result smaller → possible loss error coverage Touba, N.A., "X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISR," Test Conference, 2007. ITC 2007. IEEE International , vol., no., pp.1-10, 21-26 Oct. 2007

15. Convolutional Compactors • Space compactor with no feedback → finite impulse response • Detect errors of multiplicity 1, 2, 3 and any odd number • X resistant due to multiple output paths per input Rajski, J.; Tyszer, J.; Chen Wang; Reddy, S.M., "Convolutional compaction of test responses," Test Conference, 2003. Proceedings. ITC 2003. International , vol.1, no., pp. 745-754, Sept. 30-Oct. 2, 2003

16. Overview • ATPG • Fault-models & BIST for interconnections • Test response Compaction • Statistical timing analysis

17. Statistical Timing Analysis • Timing of nano-chipsinfluencedbyvariations of: • Tresholdvoltage of transistors (within-die, random) • Siliconsurfaceflatness (die-to-die, systematic) • Temperature, hot-spots • Variation characteristics: • Within die, withinwafer • Random, systematic • Non- vs. (spatial) correlated [1]

18. Statistical Timing Analysis • Statistical static timing analysis (SSTA) • Goal: • Predict timing yield • Techniques: • Monte-Carlo Simulations • Instantiate parameter and estimate timing for several samples • Block-based SSTA • Traverse circuit to compute PDF for outputs • Path-based SSTA • Select critical paths • Compute statistical timing

19. Statistical Timing Analysis • Modeling/Overview I. Nitta et al. Statistical static timing analysis technology. In FUJITSU Sci. Tech J., volume 43, pages 516–523, 2007. • Overview A. Srivasta et al. Statistical Analysis and Optimization for VLSI: Timing and Power. Springer Science+Business Media, Inc., 2005. • Overview/Modeling A. Agarwal et al. Statistical delay computation considering spatial correlations. In ASPDAC: Proceedings of the 2003 conference on Asia South Pacific design automation, pages 271–276, New York, NY, USA, 2003. ACM • Spatial correlated delays

20. Statistical Timing Analysis • Monte Carlo A. Srivasta et al. Statistical Analysis and Optimization for VLSI: Timing and Power. Springer Science+Business Media, Inc., 2005. • Random number generation for non-gausian distributions Anand Ramalingam et al. An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis. Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, 2006. • Path-based monte-carlo simulation

21. Statistical Timing Analysis • Block-based SSTA J.-J. Liou et al. Fast statistical timing analysis by probabilistic event propagation. In DAC ’01: Proceedings of the 38th conference on Design automation, pages 661–666, New York, NY, USA, 2001. ACM. • Agarwal et al. Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. In ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, pages 900, 2003, Washington, DC, USA, IEEE Computer Society • Preserve correlations • Compute uppper bound for CDF