Troisième Partie Chapitre 2 Instructions et adresses Pour ordinateurs séquentiels

1. Troisième Partie Chapitre 2 Instructions et adresses Pour ordinateurs séquentiels

2. Opcode Oprd. 1 Oprd. 2 Result Next Opcode Oprd. 1 Oprd. 2 Next 1 Next 2 Generic Instructions Type 1 : Data Handling Type 2 : Control ! Inefficient : address of next instruction is stored in each instruction.

3. Von Neumann Bottleneck For each data handling instruction : Central Processing Unit opcode 4 addresses 2 operands Central Memory result

4. Eliminate the “next instruction address” By using a P register Reduce size of data handling instructions By using a stack for expression evaluation By using registers for intermediate results Reduce size of control instructions By using ALU side effects stored in the condition codes register Augment work done by one instruction By using vector instructions Architectural goal 1 :Reduce the bottleneck

5. Program Counter Very often next instruction follows current one Program Memory Control Unit P register + 1 X I register

6. Program Counter (2) Type 1 : Data Handling Opcode Oprd. 1 Oprd. 2 Result Type 2 : Control Opcode Oprd. 1 Oprd. 2 Next 1 Default next address is computed in P register

7. Eliminate the “next instruction address” By using a P register Reduce size of data handling instructions By using a stack for expression evaluation By using registers for intermediate results Reduce size of control instructions By using ALU side effects stored in the condition codes register Augment work done by one instruction By using vector instructions Architectural goal 1 :Reduce the bottleneck

8. Stack Oprd. 1 / Res. Oprd. 2 Expression evaluation : Default position of operand(s) and result(s) is on the stack . . .

9. Transfer Instruction Data Handling Opcode Oprd. 1 Oprd. 2 Result Data Transfer Push/Pop Operand

10. Expression Evaluation a * ( b + c * d ) / ( e + f ) --->a b c d * + * e f + / d c * d b + c * d a*(b + c * d) c b a b a a

11. Expression Evaluation (2) a * ( b + c * d ) / ( e + f ) --->a b c d * + * e f + / f e + f a*(b + c * d) / (e + f) e a*(b + c * d) a*(b + c * d)

12. 0 vs. 3 addresses c = a + b 0 addresses pusha pushb add popc 3 addresses adda,b,c Efficiency depends on type of program

13. Eliminate the “next instruction address” By using a P register Reduce size of data handling instructions By using a stack for expression evaluation By using registers for intermediate results Reduce size of control instructions By using ALU side effects stored in the condition codes register Augment work done by one instruction By using vector instructions Architectural goal 1 :Reduce the bottleneck

14. Load/Store Reg Memory Address Registers Insert a limited number of addressable registers in the CPU to store intermediate results New data transfer instruction format

15. Registers (2) Data handling instructions become : 3 address Opcode Op 1 Op 2 Res 2 address Opcode Op 1& Res Op 2 Opcode Op 1& Res Op 2

16. Eliminate the “next instruction address” By using a P register Reduce size of data handling instructions By using a stack for expression evaluation By using registers for intermediate results Reduce size of control instructions By using ALU side effects stored in the condition codes register Augment work done by one instruction By using vector instructions Architectural goal 1 :Reduce the bottleneck

17. Condition Code Register Goal : shorten control instructions Opcode Oprd. 1 Oprd. 2 Next Into : Opcode Cond Next Z N V C evaluated  instruction

18. Eliminate the “next instruction address” By using a P register Reduce size of data handling instructions By using a stack for expression evaluation By using registers for intermediate results Reduce size of control instructions By using ALU side effects stored in the condition codes register Augment work done by one instruction By using vector instructions Architectural goal 1 :Reduce the bottleneck

19. Vector Instructions Semantics : i = 0 Result[i] := Oprd1[i] op Oprd2[i] i = i + 1 i == Count no yes

20. Vector Instructions When the same operation has to be performed on all elements of a vector Opcode Oprd. 1 (1st elt.) Oprd. 2 (1st elt.) Result (1st elt.) Count Applications : Block move in 1 or more dimensions Arithmetic and Logic operations

21. Efficient subroutine call Return address saving allowing reentrance powerful parameter passing mechanisms Efficient access to data structures Rich choice of addressing modes Efficient handling of block structured languages Efficient access to local variables Support for implementation of scope rules Architectural goal 2 :Support for High Level Languages

22. Efficient subroutine call Return address saving allowing reentrance powerful parameter passing mechanisms Efficient access to data structures Rich choice of addressing modes Efficient handling of block structured languages Efficient access to local variables Support for implementation of scope rules Architectural goal 2 :Support for High Level Languages

23. xyz : 1 jsr xyz 2 abc : abc return Subroutine Return address on stack in data memory

24. . . . . . . xyz : 1 2, 3 jsr xyz 4 abc : jsr xyz rst: rst rst return abc . . . Subroutine : Recursion . . . . . .

25. Efficient subroutine call Return address saving allowing reentrance powerful parameter passing mechanisms Efficient access to data structures Rich choice of addressing modes Efficient handling of block structured languages Efficient access to local variables Support for implementation of scope rules Architectural goal 2 :Support for High Level Languages

26. Addressing Modes How is the operand/result named ? Direct Addressing xyz xyz : Examples : jump simple operands memory

27. Addressing Modes (2) Indirect Addressing rst : xyz xyz : rst Examples : pointers call by variable . . . memory

28. xyz Addressing Modes (3) Indirect Addressing (Register) R R: xyz : Examples : pointers call by variable stack in central memory . . . memory

29. Addressing Modes (4) Relative addressing offset + base Examples : Array Record Relative jump memory

30. Efficient subroutine call Return address saving allowing reentrance powerful parameter passing mechanisms Efficient access to data structures Rich choice of addressing modes Efficient handling of block structured languages Efficient access to local variables Support for implementation of scope rules Architectural goal 2 :Support for High Level Languages

31. Block Structured Languages A program is a set of nested blocks { ... } // RED { ... } // GREEN { ... } // PURPLE { ... } // BLUE

32. int a float b char c { ... a =...; b =...; c =...; ... } X { ... a =...; b =...; c =...; ... } X { ... a =...; b =...; c =...; ... } X X { ... a =...; b =...; c =...; ... } Block Structured Languages An identifier can be used everywhere within the block where it is declared

33. int a float b char a { ... a = ‘$’; b =...; ... } X { ... a = 2; b =...; c =...; ... } X { ... a =...; b =...; c =...; ... } X X { ... a = 5; b =...; c =...; ... } Block Structured Languages A global identifier can be redefined The local definition dominates

34. Block Structured Languages The case of C, C++, Java Global block main red { ... { } } green { ... { } { } } purple { ... { } { } } No nested functions !

35. Block Structured Languages Classical block structured languages Program MyProgram Function Red { ... } Function Green { ... } Function Purple { ... } { ... } The outer block corresponds to the main program Each function (procedure) is one block

36. Variables are declared in a Block Their address has two parts: The identifier of the block The position in that block (offset) Block identifiers can be expressed by specifying relative nesting levels Block id. Rel.nesting level Offset Offset Data Addresses in Block Structured Languages

37. Variables are declared in a Block Nesting within a function can be handled statically by the compiler During execution, all local variables of a function are grouped in one block, the “activation record” of the function Addresses defined per function Function id. Offset Data Addresses in C, C++, Java

38. Data Memory Usage(1)(for C-like languages) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red … green;… GREEN; green Activation Records Operating System

39. Data Memory Usage(2) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red … green;… main GREEN; green Activation Records Return Address Operating System

40. Data Memory Usage(3) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red yellow … green;… main GREEN; green Operating System

41. Data Memory Usage(4) Global block main Data Memory : … yellow; …red;… yellow; … green; … green RED; red yellow … green;… main GREEN; green Operating System

42. Data Memory Usage(5) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red yellow … green;… main GREEN; green Operating System

43. Data Memory Usage(6) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red … green;… main GREEN; green Operating System

44. Data Memory Usage(7) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red red … red;… main GREEN; green Operating System

45. Data Memory Usage(8) Global block main Data Memory : … yellow; …red;… yellow; … green; … red RED; red red … red;… main GREEN; green Operating System

46. Data Memory Usage(9) Global block main Data Memory : … yellow; …red;… yellow; red … green; … red RED; red red … red;… main GREEN; green Operating System

47. Data Memory Usage(10) Global block main Data Memory : … yellow; …red;… yellow; … green; … red RED; red red … red;… main GREEN; green Operating System

48. Data Memory Usage(11) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red red … red;… main GREEN; green Operating System

49. Data Memory Usage(12) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red … green;… main GREEN; green Operating System

50. Data Memory Usage(13) Global block main Data Memory : … yellow; …red;… yellow; … green; … RED; red … green;… GREEN; green Operating System