Electronic Instrumentation and Measurements

1. 15 Electronic Instrumentation and Measurements

2. Computer Signal Digital Physical Sensor A/D Sampling Sensor interface phenomenon conversion computer conditioning Figure 15.1 Measurement system

3. J (+) 3 + Voltmeter connections J 1 – J ( – ) 2 Iron Constantan Copper Figure 15.3 J thermocouple circuit

4. Isothermal block + T Voltmeter 1 J ref connections J – 1 Ice T ref 0 C bath Iron Constantan Copper Figure 15.4 Cold-junction-compensated thermocouple circuit

5. v' R R + F b v b _ i i S F R 2 _ – v v R + + out v 1 R' 2 _ + v' R' a v a R' F Figure 15.16 Discrete op-amp instrumentation amplifier

6. Functional block diagram Pin Configuration 16 50 + Input 1 – Input AD625 16 – Input 15 2 + Gain sense – Gain sense 10 k RTO null RTI null – Gain Sense 15 1 1 3 14 sense 10 10 – V AD625 + V S S k k 10 k 12 – Gain 4 13 RTI null RTO null drive Output 1 0 V B – Gain drive 12 + Gain drive 5 + Gain 5 10 k drive Reference 7 Sense N/C 6 11 + Gain 10 k 2 sense Reference v 7 10 out + Input 1 + V 8 9 – V S S 50 Figure 15.18 AD625 instrumentation amplifier

7. j | H ( )| A – A A + Pass-band A min Stop-band C S Figure 15.19 Prototype low-pass filter response

8. 1.2 1 0.8 Amplitude 0.6 First order 0.4 Second order 0.2 Third order Fourth order 0 0.5 1 1.5 2 2.5 3 3.5 Normalized frequency Figure 15.21 Chebyshev low-pass filter frequency response

9. C 1 + v R R 1 2 + v v _ S C v 2 out R A R B Low-pass filter R 1 C C 2 1 + v _ S v R out 2 R A R B High-pass filter R 2 C R 1 1 v + _ S v R C out 3 2 R A R B Band-pass filter Figure 15.22 Salen and Key active filters

10. 16 14 12 10 Vd (volts) 8 6 4 2 0 0 2 4 6 8 10 12 14 16 v (volts) a Binary Quantized representation voltage v b b b b d 3 2 1 0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 14 1 1 1 0 15 1 1 1 1 Figure 15.26 A digital voltage representation of an analog voltage

11. Analog input Comparator – + Up Clock Down Up-down counter Digital output D/A Figure 15.27 Tracking ADC

12. C Clock Reset v a R – Counter – + V ref + Digital output Integrator Comparator Figure 15.28 Integrating ADC

13. “ Sample ” “ Sample input ” “ Sample input ” – v SH v v + v v a SH a SH v Voltage a follower FET C switch (buffer) Functional representation Bilateral switch Sample-and-hold of FET bilateral switch symbol for FET amplifier Figure 15.30 Description of the sample-and-hold process

14. V(t) v ( t ) a v ( t ) SH t t t t t t t t 0 1 3 4 n – 1 n 2 Figure 15.31 Sampled data

15. Control External logic clock V 1 End of Amplifier Trigger Trigger V conversion 2 Analog Sample Digital input A/D and output signals hold V 3 Internal V clock 4 Analog multiplexer Figure 15.32 Data acquisition system

16. External clock (sampling signal) t v 1 for A/D Time available t v 2 A/D t v 3 A/D t v 4 A/D t Figure 15.33 Multiplexed sampled data

17. + V S + v + out v ~ _ in – – V S v out V sat v in – V sat Figure 15.41 Transfer characteristic of zero-crossing comparator

18. + V S + v out V _ ref + v ~ in – – V S v out V sat V v ref in – V sat Figure 15.42 Transfer characteristic of inverting comparator with offset

19. v out v R R in 2 2 – V V sat sat R + R R + R 1 2 1 2 – v – v in v + out + v R 1 R 2 Figure 15.48 Transfer characteristic of the Schmitt trigger

20. V V CC CC 1 8 Ground 1 8 V 1 8 C C R 1 R 1 Trig 2 7 Disch 2 7 2 7 Trig NE555 NE555 NE555 R 2 Thresh 3 6 Out 3 6 3 6 Out Out C C Reset 4 5 Cont 4 5 4 5 NE555 pin-out 0.01 0.01 F F NE555 monostable multivibrator NE555 astable multivibrator Figure 15.61 NE555 timer