1 / 38

State of the SJTAG Initiative

State of the SJTAG Initiative. Bradford G. Van Treuren Chairman. Outline. Goal of SJTAG Changes in the Core Group Direction of the SJTAG Initiative Connect and Development Survey Activities accomplished since ITC 2005 Discussion. The Goal of SJTAG. The goal for SJTAG is:

mateo
Download Presentation

State of the SJTAG Initiative

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. State of the SJTAG Initiative Bradford G. Van Treuren Chairman SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  2. Outline • Goal of SJTAG • Changes in the Core Group • Direction of the SJTAG Initiative • Connect and Development Survey • Activities accomplished since ITC 2005 • Discussion SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  3. The Goal of SJTAG The goal for SJTAG is: for all variants of XBST and EBST, to define the data contents and formats communicated: between external Test Manager platforms and internal Embedded Test Controllers, and between Embedded Test Controllers and the UUTs they serve in an open-standard vendor-independent and non-proprietary way. SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  4. Changes Coming to Core GroupThe Chairman’s Role • Goal: Move initiative to a viable standard • Manage the expertise level of the core group • Locate new members with relevant expertise for issues needing to be addressed • Fill positions relevant to current needs • Inspire sub-teams to work on focused issues • Ensure core group stays focused on the topic • Ideal core group size needs to be 8 – 10 members to be effective • Members of core group will change over time • Sub-groups: important driving force behind SJTAG SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  5. Core Group (September 2006)Change of Leadership – Focused Resources SJTAG Core Group Brad Van Treuren, Lucent Technologies – Chair Gunnar Carlsson, Ericsson – Vice Chair Ben Bennetts, Bennetts Associates – Chair Emeritus ? ? ? ? ? ? ? Scan Support Device Vendors Test Manager Vendors System Company End Users SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  6. Structure of the SJTAG Groups Extended Group Review Group Sub-group Sub-group Core Group Sub-group SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  7. How to join • To join an SJTAG’s extended group: e-mail awareness of future events, access to archived and new documents: • Send e-mail to Brad Van Treuren, vantreuren@lucent.com • To request to join the review group or core group: complete the survey from today and indicate your desire or email your survey results to Brad Van Treuren if you did not attend. • Presentations available at www.dft.co.uk/SJTAG SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  8. Targets and Focus (10 Nov 2005 ITC Meeting) • Four main industries • Telecoms • Server/mass storage • Mil/Aero • Automotive • Need ways of describing: • The nature of the Test Manager function: all external, all embedded, distributed • The access and communication protocols • Test flow control and data requirements for test, debug, diagnosis, configuration, etc • Issues: • Security • Initial focus: telecoms, especially MicroTCA/ATCA but not exclusively. SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  9. Direction of the SJTAG Initiative • My first attempt at the Scope – Not an official statement • This standard will develop a methodology for access to test, debug, instrument, and emulation features (but not the features themselves) of devices via the IEEE 1149.1 Test Access Port (TAP) for the board and system (multiple board) domains. The elements for this methodology include a description language describing the structure of the IEEE 1149.1 connections in the system; a description of data representation formats for test vectors, diagnostic analysis, and data logging; and software application programming interfaces (APIs) defining command primitives facilitating communications between functional command, control, and data modules of a Test Manager application. • Do not use this draft as fact! SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  10. Direction of the SJTAG Initiative • My first attempt at the Purpose – Not an official statement • There is currently no defined, independent standard for this test technology. Each vendor is free in the way of implementing test hardware and software functionality on their boards. Without an independent standard, testability at the system level is reduced or impossible making the test technology in the system less useful for users integrating designs from multiple sources – limiting the ability to use the test technology in other facets of a product’s life cycle beyond manufacturing. In practice, the software used to perform test actions is written in an ad-hoc manner across the industry to access the IEEE 1149.1 features of the devices installed on the various boards of a system. Further, communications between remote and embedded hosts managing the tests applied to the system under test is non-existent or implemented using ad-hoc communications protocols. The purpose of the SJTAG initiative is to provide an extension of the IEEE 1149.1 standard specifically aimed at the configuration, control, management, and representation of the communications required at the hierarchical system and board level to perform operations on the IEEE 1149.1 Test Access Port (TAP) Controller of one or more devices, including multiple core devices, in a uniform way across all system modules. SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  11. Direction of the SJTAG Initiative • Identification of the issues to address • Current issues targeted • Diagnostics Support • Software Interfaces and API architectures • Test Languages • System Description • Develop a Use Case library to baseline ideas • Scope the work to the purpose SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  12. Core Group Focus • A. G. Lafley, CEO of Proctor & Gamble • Changed the company focus • From: 10% new product ideas provided by customers • To: 50% new product ideas provided by customers • Reframed the R&D imperative • From: “Research and Development” • To: “Connect and Development” • Now P&G is the most innovative packaged-goods marketer • For our core group to be effective, it needs innovative ideas and feedback from the extended group to make SJTAG a success SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  13. Purpose of the Survey • Survey of attendees • Provide feedback to core group members on the current issues being addressed • Provide information regarding the extended group members and interest areas in SJTAG • Provide demographics for what sectors of industry are participating in SJTAG activities • To know who we can address with questions for a particular audience • To better get to know YOU and YOUR NEEDS SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  14. Directions for the Survey • On provided paper • Write the number of the question followed by the answer • There is no need to write down the question • Each question following the first set of questions with have a single letter answer or a short description if your answer falls into the “Other” category • Example: • On Slide: What sector of the business are you affiliated with? • A. Telecom • B. Mass Storage/Servers • C. Aerospace/Military/Defense • D. Automotive • E. Tool Provider • F. Other (Please state sector) • I would answer: • A SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  15. Survey Questions • What is your name? Please print your name next to 1. on your paper. • What is your email address? Please print your email address next to 2. on your paper. • What is the name of your company? Please print the name of your company next to 3. on your paper. SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  16. Survey Questions • What sector of the business are you affiliated with? • Telecom • Mass Storage/Servers • Aerospace/Military/Defense • Automotive • Tool Provider • Other (Please state sector) SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  17. Survey Questions • What is your role with the SJTAG initiative? • Member of core group • Member of extended group • Would like to be a member of the core group because I feel I have significant skills needed by the core group and am willing to sign up for work • Would like to be a member of the review group • Would like to be a member of the extended group • Just visiting and not interested in joining a group SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  18. Survey Questions • Have you read the SJTAG White Paper? • Yes • No • An SJTAG Test Manager is: • An external system for generating and managing tests • A hardware interface between the microprocessor and the boundary-scan infrastructure on the board • Any combined hardware/software test control system • None of the above SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  19. Survey Questions • An SJTAG Test Controller is: • A hardware interface between the microprocessor and the boundary-scan infrastructure on the board • Some or all of the functionality of a runtime-control Test Manager that is built into the UUT • Any combined hardware/software test control system • None of the above SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  20. Survey Questions • A JTAG Protocol Manager (JTAG-PM) is: • Handshake protocol between a Test Manager and a Test Controller • Any combined hardware/software test control system • A hardware interface between the microprocessor and the boundary-scan infrastructure on the board • None of the above SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  21. Survey Questions • The term EBST stands for: • External Boundary Scan Test • Embedded Boundary Scan Test • Embedded Board Self Test • Enhanced Boundary Scan Test • None of the above SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  22. Survey Questions • Do you implement Boundary-Scan as a test process for your system-level test now? • Yes • No • N/A • Do you anticipate the use of Boundary-Scan test at the system-level in the future for your systems? • Yes • No • N/A SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  23. Survey Questions • I feel SJTAG is: • Predominantly a “Software” issue and is NOT a Hardware and Architectural one. • Predominantly a “Hardware” issue and is NOT a Software and Architectural one. • Predominantly an “Architectural” issue and is NOT a Hardware and Software one. • An even mix of Software, Hardware, and Architectural issues. • A even mix of Software and Hardware issues and less of an Architectural issue. • An even mix of Software and Architectural issues and less of a Hardware issue. • An even mix of Hardware and Architectural issues and less of a Software issue. SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  24. Survey Questions • I feel that tests need to be managed (e.g. Test Manager role) • Entirely within my system • Entirely from an external system • Primarily from within my system with provisions to add additional tests on request • Primarily from an external system with provisions to run stand-alone within my system • Tool suppliers: Please indicate what you feel your tools need to support SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  25. Survey Questions • What level of diagnostics do you need from an SJTAG based system? • GO/NO-GO • Device Pin and Net Failure information • Pin Faults (stuck-at, shorts, opens) • Diagnostic analysis needs to be performed: • In the system. • Real-time from a remote computer. • Off-line from a remote computer. SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  26. Survey Questions • Do you feel emulation support at the system-level is important to you? • Yes • No • Do you feel board-level access to instrumentation inside devices is important? • Yes • No • Do you feel system-level (multiple board) access to instrumentation inside devices is important? • Yes • No SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  27. Survey Questions • The test language I primarily use for Boundary-Scan test application is: • SVF • STAPL • Other (Please state what language that is) SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  28. Activities accomplished since ITC 2005 • May 2006 SJTAG Meeting at EBTW2006 • Demonstration of an example Test Manager/Test Controller coordinated test system • Presentation from Test Manager Developer (Adam Ley) • Presentation from Test Controller Developer (Peter Horwood) • Presentation from Motorola and their perspective of SJTAG (Stephen Harrison) SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  29. Demo Shown at EBTW May 2006 Full Diagnostics Return format SVF JTAG Module Chains SVF Test Manager BVR Translator BVR2 STAPL μP Firecron Diagnostics Chain Selector OTHER? JTAG Controller First level Interchangeability Gateway ASSET’s ScanWorks Firecron’s BVR file Single board Firecron’s FSC-1000 Controller Ethernet link SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  30. Activities accomplished since ITC 2005 • September 2006 SJTAG at BTW2006 • Demonstration of Lucent embedded device pin and net failure reporting from their Lucent Test Flow Control Language™ (TFCL™) • Presentation of an SJTAG Interface Perspective • Discussion on diagnostic representation alternatives • Discuss relationship between IJTAG and SJTAG SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  31. Apply a set of vectors Capture a set of responses Compare responses to known expected values Conditionally apply next set of vectors based on response result of PASS or FAIL Fixed set of tests that are applied over and over again Application Test Package and Test Program Flow Control (Ordered collection of Test Programs) Test Programs and Test Step Flow Control (Ordered collection Of Test Steps) Test Steps (Ordered collection of Scan and PIO Operations) 1149.1 Scan Operations (Represents Leaf Functions as Vector Patterns) Test Access Port Controller Operations Layers of the Software for Traditional EBST Test Manager ? Test Controller SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  32. Application Test Package Interface Test Package and Test Program Flow Control (Ordered collection of Test Programs) Test Program Interface Test Programs and Test Step Flow Control (Ordered collection Of Test Steps) Test Step Interface Test Steps (Ordered collection of Scan and PIO Operations) Scan Interface 1149.1 Scan Operations (Represents Leaf Functions as Vector Patterns) TAP Interface Test Access Port Controller Operations Interface Boundaries of the Software Potential Standardization of Interface STAPL SVF SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  33. SJTAG Data PerspectiveInterconnect ATPG Example – Data Representation • Net – Device Pin – Device Cell – Chain Cell • Databases store data in tables • Related information contained on same row • Can we use a table for diagnostic data storage in EBST? SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  34. IJTAG Relationship with SJTAG • IJTAG provides an interface bridge for a device package between embedded instruments and the external JTAG port of the device package • IJTAG is an extension of the IEEE 1149.1 standard aimed at using the TAP to manage the configuration, operation, and collection of data from embedded instrumentation circuitry inside a device package • IJTAG defines the data file format necessary to describe the instrumentation configuration, operation, and data registers that are accessible from the TAP for tools to generate commands for the instrument (i.e., BSDL for instruments) SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  35. IJTAG Relationship with SJTAG • SJTAG defines an interface methodology from external or embedded test systems to boards/blades installed in a system • SJTAG defines an interface methodology from embedded test systems on boards to the device packages located locally on the board or daughter boards • SJTAG defines an interface methodology from external or embedded test systems to the device packages located in system (The IJTAG world) SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  36. IJTAG Relationship with SJTAG • SJTAG defines the software interfaces between layers of the interface methodology • SJTAG defines the data description formats that describe the JTAG interface definition for each IEEE 1149.1 architectural module in the system SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  37. IJTAG Bridge Core w/ Instrument 1500 Wrapper TAP Controller IJTAG Relationship with IEEE 1500 • IJTAG provides a bridge interface from the device package JTAG port to embedded instruments • The 1500 wrapper for core features are considered one of the IJTAG specialized instruments • The IJTAG bridge interfaces directly with the 1500 wrapper as the Test Access Mechanism (TAM) control logic • IJTAG provides the control, operation, and register access to the 1500 wrapper using the 1149.1 TAP interface of the device package TAP Interface SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

  38. Your Turn Q & A SJTAG Fringe Meeting – October 2006 ITC 2006, Santa Clara, CA

More Related