Transient Analysis of Power System

1. Transient Analysis of Power System Chung-Kuan Cheng January 27, 2006 Computer Science & Engineering Department University of California, San Diego

2. Outline • Statement of the Problem • Status of Simulators • Solver Engine: Multigrid Review • Integration Method • Frequency Domain Analysis • Experimental Results • Conclusion

3. Statement of Problem • Huge RLC linear system with multiple sources • Wide spread of natural frequencies (KHz-GHz) • Many corners and many modes of operations • Packaging and transmission lines • Nonlinear devices

4. Status of the Simulator • Matrix Solvers: Multigrid, Multigraph • Integration Method: Operator Splitting • Frequency Domain Analysis

5. High Complexity Basic Iterative Method Slow Convergence Multigrid Method MultiGrid, MultiGraph Conjugate Gradient Matrix Solvers Direct Method LU, KLU

6. Multigrid Review • Error Components • High frequency error (More oscillatory between neighboring nodes) • Low frequency error (Smooth between neighboring nodes) • Basic iterative methods only efficiently reduce high frequency error • Basic Idea of Multigrid • Convert hard-to-damp low frequency error to easy-to-damp high frequency error

7. A2•X2=b2 A1 •X1=b1 A0 •X0=b0 1 4 1 2 6 3 2 5 3 4 1 Multigrid : A Hierarchy of Problems 2 Gauss Elimination Interpolation Restriction Smoothing Smoothing Interpolation Restriction Smoothing Smoothing Hierarchically, all error components smoothed efficiently

8. Geometric vs Algebraic • Geometric multigrid method • Require Regular Grid Structure • Algebraic Multigrid • Coarsening Relied on Matrix, • No requirement of regular grid structure • Coloring scheme • Error Smoothing Operator: Gauss-Seidel • Interpolation • Small residue but the error decreases very slowly. • In practice, we use only coarse node at the RHS of above formula to approximate error correction of fine node.

9. System Equation: Apply Trapezoidal Rule: Convergence of Multigrid Method • RLKC network The LHS matrix is not S.P.D, but can be converted to S.P.D matrix The LHS matrix of first equation is now S.P.D. Similar for B.E and F.E L-1 is called K / Susceptance / Reluctance Matrix

10. Experimental Results (1) • IBM Test Case • Board / Packaging / Chip Power Network • Fully coupled packaging inductance • 60k elements, 5000 nodes. • Spice failed • Our tool • Less than 10 minutes chip board Power Supply

11. Experimental Results (2) • Power/Clock network case from OEA Tech. • 30k nodes, 1000 transistor devices • HSPICE/Spice run more than 2 days on our 400M Solaris machine (Sun Blade 100) • Our Run time: 1.5 hour

12. Integration Method:Operator Splitting • ADI: Two way partitions. Working on time steps. • Operator Splitting: Multiway Partitioning. Research + Development.

13. Operator Splitting- A Simple Example Initial value problem (IVP) of ordinary differential equation (ODE) where L is a linear/nonlinear operator and can be written as a linear sum of m subfunctions of u Suppose are updating operators on u from time step n to n+1 for each of the subfunctions, the operator splitting method has the form of:

14. General Operator Splitting on Circuit Simulation • We generalize the operator splitting to graph based modeling • No geometry or locality constrains • Convergence • A-stable: independent of time step size • Consistence : local truncation error

15. Spice Formulation - Forward Euler Circuit Equation for RLC circuits: Forward Euler Formulation where

16. Spice Formulation – Backward Euler Circuit Equation for RLC circuits: Backward Euler Formulation where

17. Splitting Formulation Split the circuit resistor branches into two partitions, we have Each partition has a full-version of capacitors and inductors.

18. Splitting Formulation General Operator Splitting Iteration: Alternate Backward and forward integration on partitions

19. Circuit Splitting: Splitting Algorithm • Objective • Minimize the overall nonzero fill-ins • Guarantee DC path for every nodes • Hint: • Tree structure generate no nonzero fill-ins in LU factorization. • High Degree nodes generates more nonzero fill-ins during LU factorization • Linear Circuits (talk about circuits with transistors later) • Bipartition of neighbors for each node • Basic idea • In the LU decomposition process, non-zero fill-in will be introduced among neighbors of the pivot. Reduce the number of neighbors for all nodes will be beneficial to decrease the number of non-zero fill-ins. • Avoid loop, make tree structure as much as possible • Check DC path, reassign partition if necessary

20. Power Network & Gate Sinks Experimental Results-1 Voltage Drop of Circuit3

21. Experimental Results-2 • RLC Power/Clock network case. • 29110 nodes, 720 transistor devices • Spice3 Runtime: 12015 sec. • Our Run time: 649.5 sec. 18.5x

22. Experimental Result-3 Two 1K and 10K cell designs Bottle neck: Nonzero fill-ins Device Evaluation Time

23. Large Power Ground Network • 600,000 nodes • Irregular RC network • 10ns Transient Simulation: 4083sec

24. Frequency Domain Analysis • Natural Frequency Extraction • Complex Matrix Solver • Fast Fourier Transformation

25. Conclusion • Transient of Power Analysis: Post Doc. (Sep 05-Feb 06) • Nonlinear Network: Fastrack Release • Operator Splitting: Rui Shi • Packaging: Vincent Peng • Frequency Domain Analysis: R. Wang

26. References • Efficient Transistor Level Simulation Using Two-Stage Newton-Raphson and Multigrid Method,CK Cheng and Zhengyong Zhu, filed by UCSD, SD2005-013. • Circuit Splitting in Analysis of Circuits at Transistor Level, C.K. Cheng, R. Shi, and Z. Zhu, filed by UCSD, SD2005-129-PCT, June 7, 2005. • Z. Zhu, B. Yao, and C.K. Cheng, "Power Network Analysis Using an Adaptive Algebraic Multigrid Approach, ACM/IEEE Design Automation Conference, pp. 105-108, June 2003. • Z. Zhu, K. Rouz, M. Borah, C.K. Cheng, and E.S. Kuh, "Efficient Transient Simulation for Transistor-Level Analysis,“ Asia and South Pacific Design Automation Conf., 240-243, 2005.