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Introduction to ADI BF53X Instruction Set

Introduction to ADI BF53X Instruction Set. 謝文雯 李岳叡 陳柏元 楊侑儒. Outline. Key Features of the Blackfin Architecture Overview Parallelism Instruction Set. Key Features of the Blackfin. 16-bit fixed-point dual-MAC processor Orthogonal RISC-like microprocessor instruction set

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Introduction to ADI BF53X Instruction Set

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  1. Introduction to ADI BF53X Instruction Set 謝文雯 李岳叡 陳柏元 楊侑儒

  2. Outline • Key Features of the Blackfin • Architecture Overview • Parallelism • Instruction Set

  3. Key Features of the Blackfin • 16-bit fixed-pointdual-MAC processor • Orthogonal RISC-like microprocessor instruction set • Mixed-width 16-/32-bit instruction set • Load / Store architecture • Flexible SIMD capabilities • Multimedia features • Limited VLIW capability

  4. Architecture Overview • Data arithmetic unit • computational units (two fixed-point data paths) • data register file • Address arithmetic unit • two DAGs • pointer register file • data address generator (DAG) registers • Control unit • sequencer, align, decode, loop buffer

  5. Register Files (1/4) • Data register (Dreg7-0) • for the computational units • Pointer register (Preg5-0, SP, FP) • for address calculation • for general integer arithmetic • DAG register (I3-0, M3-0, B3-0, L3-0) • for addressing in DSP instruction • Index register (Ireg) • Modify register (Mreg) • Base register(Breg) • Length register (Lreg)

  6. Register Files (2/4)

  7. Register Files (3/4) • Accumulators (A0, A1) • 40 bits wide • An.X[39:32], An.H[31:16], An.L[15:0] • An.W[31:0] • An[39:0]

  8. Register Files (4/4) • System registers • for zero-overhead loop • LC0, LC1 : loop counter • LT0, LT1 : top address of loop • LB0, LB1 : bottom address of loop • for RETURN • RETS, RETI, RETX, RETN, RETE

  9. Parallelism • Possible combinations of instruction issuing

  10. Instruction Set • Program Flow Control • Load / Store • Move • Stack Control • Control Code Bit Management • Logical Operations • Bit Operations • Shift / Rotate Operations • Arithmetic Operations • Video Pixel Operations • Vector Operations

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