Joining the Design and Mask Flows for Better and Cheaper Masks

1. Joining the Design and Mask Flows for Better and Cheaper Masks Andrew B. Kahng (abk@cs.ucsd.edu) Puneet Gupta (puneet@ucsd.edu)

2. Outline • Introduction • Design Aware OPC • Placement for Better DOF • Gate Length Biasing • Tying CMP and OPC • Design-Based Qualification of RET

3. Today’s Design-Manufacturing Interfaces Design Rules Device Models Library (Library Team) Litho/Process (Tech. Development) Layout & libs (Corner Case Timing) RET Mask: Dataprep (Mask House) Design (ASIC Chip) Layout (collection of polygons ?) Tapeout Guardbanding all the way in all stages!! (e.g. clock ACLV guardband ~ 30%) • What do we lose ? • Performance  Too much worst-casing • Turnaround time  Huge OPC runtimes, overdesign • Predictability  RET is applied post-design • Mask costs  Overcorrection • Designer’s intent lost  RET is not driven by design

4. Foundation of the DFM Solution • Bidirectional design-manufacturing data pipe • Fundamental drivers: cost, value • Pass functional intent to manufacturing flow • Example: RET for predictable timing slack, leakage, yield • RETs should win $$$, reduce performance variation •  cost-driven, parametric yield constrained RET • Pass limits of manufacturing flow up to design • Example: avoid corrections that cannot be manufactured or verified  e.g., design should be aware of metrology N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/

5. Outline • Introduction • Design Aware OPC • Placement for Better DOF • Gate Length Biasing • Tying CMP and OPC • Design-Based Qualification of RET

6. OPC and Design Intent: Many Known Opportunities • OPC applied post-tapeout • Overcorrection (matching corners)  mask cost • Large runtimes • Impact of OPC on performance unknown • Designer’s intent: OPC quality metrics • CD (Poly over active) • Non-critical poly need not be well-controlled • Contact Coverage • “Perfect” corners unnecessary if there is enough contact overlap • Line end shortening  Poly should not “cut into” active

7. Today’s OPC and Design Intent • Annotate features with “required amount” of OPC • E.g., why correct dummy fill? • Determined by design intent • E.g., setup and hold timing slacks, parametric yield criticality of devices and features • Goal: reduce total OPC inserted (e.g., SRAF usage) •  Decreased physical verification runtime, data volume •  Decreased mask cost resulting from fewer features • Supported by formats (OASIS, IBM GL-I, OA/UDM) • Design-to-mask tools need to make and use annotations

8. “Design for Value” in the OPC Context Given: Admissible levels of (OPC) correction for each layout feature, and corresponding delay impact (mean and variance) Find: Level of correction for each layout feature, such that a prescribed selling point delay is attained Objective:Minimize total cost of mask corrections

9. MEBES Volume vs. Gate CD Error • Total post-fracturing MEBES data volume averaged over all cells in Artisan TSMC libraries (130nm, 90nm) • Model-based OPC and fracturing by Calibre

10. Potential Mask Data Reduction • Difference in data volume between 4%, 24% CD error • 90nm flow and data volume include SRAF insertion

11. Traditional OPC Flow Updated OPC Flow Testcase CD Distribution OPC Delay CD Distribution OPC Delay Normalized All Gates (nm) Runtime (ns) All Gates (nm) Critical Gates (nm) Runtime (ns) MEBES s s s mean (s) mean mean (s) Volume alu128 126.1 1.48 51516 3.28 131.5 4.93 130.8 2.04 33535 3.28 0.76 c7552 126.2 1.89 7149 1.59 132.0 4.77 130.1 1.99 5142 1.59 0.78 c6288 126.0 1.37 12830 5.21 131.4 4.45 129.7 1.27 9710 5.21 0.82 c5315 126.1 1.82 4539 1.94 131.7 4.70 129.7 1.89 4247 1.94 0.79 c432 126.8 1.57 1020 1.33 131.3 3.90 129.9 1.67 737 1.33 0.83 New Tool Savings testcase Run time Mask data alu128 35% 24% c7552 28% 22% c6288 24% 18% c5315 6% 21% c432 28% 17% Performance-Driven OPC (130nm) • Notes: • Early experimental results based on subset of available optimizations • Same worst-case delay (corner-based STA) • Preserves CD tolerance for critical gates • Mask data savings shown result from gate poly optimization only. Results will improve substantially with inclusion of field poly and metal layers. • Runtime savings shown do not include pattern-based OPC technology under development Thanks: Dennis Sylvester and Jie Yang, Univ. of Michigan

12. # of features Degree of correction The OPC Tug-of-War Increasing yield loss Increasing mask cost # of features Better yield Cheaper masks Our Tool Degree of correction • Current OPC situation • Degree of correction is global compromise between mask cost and yield loss • Many chip features are over corrected, some are under corrected • Sub-optimal for both yield and cost • A New Tool (i.e., our tool): • Customized correction target per cell instance • Automatically computed based on timing and yield analysis • Superior solution for both yield and cost

13. Design Aware OPC for Better Yield • Obtain signed EPE tolerances and acceptable direction of variation from design power/performance constraints • E.g., a setup-constrained gate has a constrained +ve EPE tolerance, a recommended –ve tolerance due to leakage with acceptable direction being gate CD getting smaller • Obtain direction of CD variation of the features with defocus  if not same as above, flag • Design aware fragmentation • Finer fragmentation for smaller tolerance features • Result: Tradeoff OPC effort in non-critical regions of layout with critical geometries • Potential fallback: some loss in hierarchy • Another example: dual damascene vias have high resistivity barrier on bottom  coverage of “up” vias more important than “down” vias

14. Outline • Introduction • Design Aware OPC • Placement for Better DOF • Gate Length Biasing • Tying CMP and OPC • Design-Based Qualification of RET

15. Assist Features and Variation SB = Scattering Bar  SRAF 0.22 • SRAFs are dummy geometries • Improve process window overlap for dense and isolated features • Not supposed to be printed • Unavoidable for 90nm poly 0.2 0.18 0.16 CD 0.14 0.12 0.1 0.08 2 SB 1 SB W/O SB DOF 0.06 0.04 0.0 0.1 0.2 0.3 0.4 0.5 0.6 SB2 No SB SB1 Thanks: Chul-Hong Park, UCSD

16. Layout Composability for SRAFs • Feature spacings are restricted to a small set • Two components • Assist-correct library layouts  Inter-device spacing within a standard cells  Intelligent library design • Assist-correct placement  space between cells needs to be adjusted  Intelligent whitespace management Better than  x  x+dx

17. Cell boundary Forbidden pitch Before AFCorr After AFCorr Example

18. SB=2 SB=3 SB=4 SB=1 allowable forbidden Forbidden Pitch Rules Pitch (X:um) #SRAF = 0 0<=X<0.51 #SRAF = 1 0.51<=X<0.73 #SRAF = 2 0.73<=X<0.95 #SRAF = 3 0.95<=X<1.17 #SRAF = 4 1.17<=X Forbidden pitches Bias OPC [0.37, ∞] SRAF OPC [0.37, 0.509], [0.635, 0.729],[0.82, 0.949],[1.09, 1.16]

19. Experimental Results • The number of total SRAFs increases due to AFCorr benefit even though the benefit decreases in the lower utilization. • At the same manner, number of EPE and forbidden pitch is reduced in 130nm and 90nm technology nodes.

20. Outline • Introduction • Design Aware OPC • Placement for Better DOF • Gate Length Biasing • Tying CMP and OPC • Design-Based Qualification of RET

21. Multi-Lgate Design for Leakage • Lgate biasing from 130nm to 140nm • Leakage benefit = 29% • Delay overhead = 5% ; Dynamic power overhead = 3.5% • Potential alternative/supplement to multi-Vt design • Avoid high variability in low Vt and manufacturing overheads of multi-Vt • CD variability (as a %) is less for larger Lgate design Thanks: Puneet Sharma, UCSD

22. Gate-Length Biasing Biasing • Reduces leakage variability • Can be implemented transparent to design in the MDP flow • Potential side benefit of a larger process window for biased gates for the same pitch

23. Results: Leakage Reduction With less than 2.5% delay penalty • Design Compiler used for VT assignment and gate-length biasing • Better results expected with better sizers Thanks: Puneet Sharma, UCSD

24. Percentage Reduction in Leakage Spread Results: Leakage Variability • Biasing  “flatter” region of Lgate-leakage dependence • Leakage distribution for the testcase alu128 (500 samples) • Traces shown • Unbiased circuit • Technology level biasing • Uniform biasing

25. Outline • Introduction • Design Aware OPC • Placement for Better DOF • Gate Length Biasing • Tying CMP and OPC • Design-Based Qualification of RET

26. CMP • Chemical-Mechanical Planarization (CMP) • Polishing pad wear, slurry composition, pad elasticity make this a very difficult process step silicon wafer slurry feeder wafer carrier polishing pad slurry polishing table Post-CMP ILD thickness Features Area fill features Depth of focus budgets are the biggest determinants of planarization budgets and in turn hard to achieve (and detrimental to performance) density constraints

27. CMP Aware OPC • Compute local defocus from CMP simulation of underlying layer • CMP simulation can be as simple as density based models • Divide layout GDS into defocus regions and run model-based OPC on each region with different “best-focus” condition • In case of unavailability of defocus models, simple “right direction” biasing may help • Advantages: • Better depth of focus • Less stringent CMP requirements • More relevant for Metal 1 and above • Possible design implications: • Enforced regularity on metal layers (less stringent than “single pitch” though) • Tighter density control on pre-identified timing critical regions

28. Outline • Introduction • Design Aware OPC • Placement for Better DOF • Gate Length Biasing • Tying CMP and OPC • Design-Based Qualification of RET

29. OPC Quality Verification • ORC does “shape” checks only • E.g., shorting of redundant vias is not a fault • A post-RET LVS is needed to avoid false fails • Power/performance qualification • Post-RET leakage/dynamic power/timing analyses • Reliability qualification • Check for “necking”, small vias and other EM hotspots • Catastrophic yield qualification • Critical area analysis on simulated wafer images • Concept of “design process window” • Constant X% CD tolerance for PW computation is overkill  PW-critical features may not be timing critical • Compute PW over timing paths rather than individual features

30. Conclusions • Several optimizations and simplifications of RET flow possible with design input • We have not even talked about design-awareness in mask inspection • MDP can help increase parametric yield • Gate length biasing decreases leakage variability • Process window improvements by design input • CMP-driven OPC • Timing aware “true” process windows • RET quality of result • Simple “geometric” ORC not enough • Explicit awareness of designer metrics like power, performance, yield and reliability is needed