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Hardware Accelerators Project

Characteristic Presentation. Hardware Accelerators Project. Students : Supervisor : Duration :. Zakharenko Vitaly and Alex Tikh Inna Rivkin Single semester. General project goals. Optimized implementation of radar pulse sequence deinterleaving algorithm on FPGA. System specifications.

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Hardware Accelerators Project

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  1. Characteristic Presentation Hardware Accelerators Project • Students: • Supervisor: • Duration: Zakharenko Vitaly and Alex Tikh Inna Rivkin Single semester

  2. General project goals Optimized implementation of radar pulse sequence deinterleaving algorithm on FPGA

  3. System specifications Goal system functionality • Receives a noised mix of radar pulse sequences of different periodicities. • Extracts pulse sequences from the mix, supplies periodicity of each sequence.

  4. General implementation procedure • Implementation of an Altera SOPC Builder system comprised of a single NIOSprocessor component and a number of C2H generated accelerator components for radar pulse deinterleaving • Optimization of the above system

  5. General C2H acceleratedSOPC system diagram

  6. Step I: Design Detailed implementationprocedure 1. Design of an SOPC Builder system containing one NIOS processor component 2. Coding the algorithm in C 3. Profiling and identifying code segments requiring acceleration 4. Generation of C2H HW accelerators for such code segments 5. Choosing optimal interface and protocol for communication with the packet switch implemented by other teams

  7. Step II: Optimization Detailed implementationprocedure 1. Optimizing the implementation with respect to memory interconnects and C2H performance parameters (CPLI, latency). 2. Optimizing the number of C2H accelerator components connected to the same NIOS processor. 3. Optimizing NIOS processor component parameters

  8. Schedule • Week 1: coding the algorithm in C • Week 2: generating a single set of C2H accelerators, defining the interface with the packet switch component • Week 3-4: optimization of the set of accelerators • Week 5-6: choosing optimal number of accelerators connected to the same NIOS processor

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