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MTJ Design Space

MTJ Design Space. Design Space v3. MTJ Data (Zhongming). Data supports modeling MTJ variation as a nominal R P and TMR with some σ Rp and σ TMR. MTJ Scaling. Critical Switching Current: If we scale MTJ dimensions to keep Δ constant, then:

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MTJ Design Space

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  1. MTJ Design Space Design Space v3

  2. MTJ Data (Zhongming) • Data supports modeling MTJ variation as a nominal RP and TMR with some σRp and σTMR.

  3. MTJ Scaling • Critical Switching Current: • If we scale MTJ dimensions to keep Δ constant, then: (Note: scaling MTJ dimensions theoretically has no effect on TMR)

  4. RP vs. WN for Fixed IC Traces (Fengbo)

  5. Bounds: RP & RAP (TMR) • Upper bounds: Maximum resistance to support minimumdesired write current • Empirically derived for RP & RAP for a given cell size

  6. IBM90nm: RP vs. WN [RP]

  7. IBM90nm: RP vs. WN [RAP]

  8. IBM65nm: RP vs. WN [RP]

  9. IBM65nm: RP vs. WN [RAP]

  10. IBM45nm: RP vs. WN [RP]

  11. IBM45nm: RP vs. WN [RAP]

  12. 65nm Design Space Examples

  13. 65nm Design Space Example [FLASH] • Target Performance: • Write Time: 100µs-10ms • Read Time: < 10µs • Cell Size: 6F2 ~ WN = 0.10µm • MTJ Device Characteristics (Sample Distribution): • RA = 5Ωµm2 • TMR = 110% • Δ = 50 • For 1ns switching with L = 170nm &W = 50nm • IP→AP ≥ 375μA • IAP→P ≥ 550μA • CELL SIZE TOO SMALL → BETTER MTJs NEEDED

  14. 65nm Design Space Example [eDRAM] • Target Performance: • Write Time: 5-10ns • Read Time: <10ns • Cell Size: 30F2 ~ WN = 0.50µm • MTJ Device Characteristics (Sample Distribution): • RA = 5Ωµm2 • TMR = 110% • Δ = 50 • For 1ns switching with L = 170nm &W = 50nm • IP→AP ≥ 375μA • IAP→P ≥ 550μA

  15. 65nm: Nominal [eDRAM] • No Boosting • Wn = 0.50μm (30F2) • Write Time: 10ns • MTJ (Nominal): • IP→AP ≥ 358μA • IAP→P ≥ 525μA • RP = 749Ω • RA = 5 [Ωμm2] • L = 170 [nm] • W = 50 [nm] • TMR = 110%

  16. 65nm: MTJ Scaling [eDRAM] • No Boosting • Wn = 0.50μm (30F2) • Write Time: 10ns • MTJ (S = 0.75): • IP→AP ≥ 232μA • IAP→P ≥ 341μA • RP = 1332Ω • RA = 5 [Ωμm2] • L = 128 [nm] • W = 38 [nm] • TMR = 110%

  17. 65nm: MTJ & RA Scaling [eDRAM] • No Boosting • Wn = 0.50μm (30F2) • Write Time: 10ns • MTJ (S = 0.75): • IP→AP ≥ 232μA • IAP→P ≥ 341μA • RP = 799Ω • RA = 3 [Ωμm2] • L = 128 [nm] • W = 38 [nm] • TMR = 110%

  18. 65nm: Boosting [eDRAM] • Boosting • Wn = 0.50μm (30F2) • Write Time: 10ns • MTJ (Nominal): • IP→AP ≥ 358μA • IAP→P ≥ 525μA • RP = 749Ω • RA = 5 [Ωμm2] • L = 170 [nm] • W = 50 [nm] • TMR = 110%

  19. 65nm: Boosting & MTJ Scaling [eDRAM] • Boosting • Wn = 0.50μm (30F2) • Write Time: 10ns • MTJ (S = 0.90): • IP→AP ≥ 306μA • IAP→P ≥ 448μA • RP = 925Ω • RA = 5 [Ωμm2] • L = 153 [nm] • W = 45 [nm] • TMR = 110%

  20. 65nm Design Space Example [SRAM] • Target Performance: • Write Time: ~1ns • Read Time: <5ns • Cell Size: 120F2 ~ WN = 2.00µm • MTJ Device Characteristics (Sample Distribution): • RA = 5Ωµm2 • TMR = 110% • Δ = 50 • For 1ns switching with L = 170nm &W = 50nm • IP→AP ≥ 375μA • IAP→P ≥ 550μA

  21. 65nm: Nominal [SRAM] • No Boosting • Wn = 2.00μm (120F2) • Write Time: 1ns • MTJ (Nominal): • IP→AP ≥ 375μA • IAP→P ≥ 550μA • RP = 749Ω • RA = 5 [Ωμm2] • L = 170 [nm] • W = 50 [nm] • TMR = 110%

  22. 65nm: MTJ Scaling [SRAM] • No Boosting • Wn = 2.00μm (120F2) • Write Time: 1ns • MTJ (S = 1.30): • IP→AP ≥ 556μA • IAP→P ≥ 815μA • RP = 443Ω • RA = 5 [Ωμm2] • L = 221 [nm] • W = 65 [nm] • TMR = 110%

  23. 65nm: Boosting [SRAM] • Boosting • Wn = 2.00μm (120F2) • Write Time: 1ns • MTJ (Nominal): • IP→AP ≥ 375μA • IAP→P ≥ 550μA • RP = 749Ω • RA = 5 [Ωμm2] • L = 170 [nm] • W = 50 [nm] • TMR = 110%

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