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The AMD K8 Processor Architecture

The AMD K8 Processor Architecture. December 14 th 2006. K7 vs K8. K7: 3 x86 decoding units, 3 integer units (ALU), 3 floating point units (FPU),128KB L1 cache K8: 3 decoders (16 bytes of instructions per clock cycle); x86 instructions decoded into fixed length micro-operations (µOPs).

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The AMD K8 Processor Architecture

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  1. The AMD K8 Processor Architecture December 14th 2006

  2. K7 vs K8 K7: 3 x86 decoding units, 3 integer units (ALU), 3 floating point units (FPU),128KB L1 cache K8: 3 decoders (16 bytes of instructions per clock cycle); • x86 instructions decoded into fixed length micro-operations (µOPs). • Complex instructions are decoded into 2 + µOps • FastPath: Certain µOPs are packed together • µOPs are then dispatched to the execution units. • 3 Address Generation Units (AGU) for Loads and Stores • Three integer units (ALU): most µOps executed in one cycle, multiplication has a 3 cycles latency in 32 bits, and a 5 cycles latency in 64 bits • Three floating point units (FPU), that handle x87, MMX, 3DNow!, SSE and SSE2 instructions • Load/Store stage: The L1 is dual-ported, that means it can handle two 64 bits reads or writes each clock cycle

  3. K8 Hammer Microarchitecture

  4. K7 vs K8 Pipelines

  5. K8 L1 and L2Cache The L1 cache The L2 cache

  6. Exclusive vs Inclusive Cache

  7. K8 Athlon 64

  8. Athlon 64 Operating Modes

  9. Opteron VS. Xeon

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