RAL ASIC Design & RD53 IP WG

1. RAL ASIC Design & RD53 IP WG • Presenter: Mark Prydderch • ASIC Design Group Leader • Science & Technology Facilities Council • Rutherford Appleton Laboratory • Harwell Oxford • Didcot • Oxfordshire • OX11 0QX • United Kingdom

2. RAL ASIC Design Group • Mark • Prydderch • Davide • Braga • Lawrence • Jones • Stephen • Thomas • Stephen • Bell • Michelle • Key-Charriere • Quentin • Morrissey • Rebecca • Coath • HEXITEC • CMS Binary Chips • 130 & 65nm Development • CDS ADC, STAR & C2BA • R3B • ATLAS ABC130 & HCC • 21.4 x 20.1mm • 6400 Pixels • XFEL LPD • 7 x 4mm, • 254 Channels, • 256 deep pipeline • 10.8 x 4.8mm, • 128 Channels, • Timestamp, • 12b ADC • 16b ADC • 10b DAC • Bias & Telemetry • 14.5 x 7.3mm, 512 pixels, • 1536 x 512 analogue memory • 16x12b ADC • 10.8 x 4.8mm, • 254 Channels, • Correlation Logic • 256 deep pipeline

3. Example: CDS ADC • Features • DC Restoration of the CCD video signal. • Fully differential-input preamplifier and CDS. • 1 V video signal input range. • Fully differential pipelined 16 bit ADC with digital error correction. • Operation at up to at least 2 Mpixels/s • 10 bit Programmable Offset (+/- 500 mV). • 7 bit Programmable Gain (gain = x 1 to x 3) • Input referred system noise  3.5 adurms • 3-wire serial interface to program video gain & offset. • Triple-voting control Logic to protect against SEUs.

4. IP participation • Clear ideas on how IP libraries should be developed and managed (see Talk by Stephen Bell). • Interested to hear ideas/thoughts of other groups. • We aim to put this into practice with our own internal development programme in 2014. • Interested in developing the ‘Self Biasing Rail to Rail Amp for Bias distribution’. • Would seek an RD53 partner for the radiation testing.

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