Lecture 9 RX210 Introduction & I/O Ports

1. Lecture 9 RX210 Introduction & I/O Ports

2. Outline • RX Series Introduction • RX210 Core • RX210 Architecture • RX210 Interrupt Vector Table • RX210 Bus Configuration

3. What is MCU? (微型) M icro- (控制器) C ontroller (單元) U nit

4. RX Platform Road Map • Expanding the platform at both low-end and high-end to re-enforce family concept and minimize customers’ development cost. 40nm process w/ RXv2 core (enhanced FPU and DSP) Planning 40nm process w/ RXv2 core ( enhanced FPU and DSP ) NEW Leading edge Performance Up to 4MB Flash and 512kB RAM High Performance, Integration Up to 4MB Flash and 512kB RAM WS: 2Q14 RX600 RX640 High Performance, Integration up to 2MB Flash and 256kB RAM RX700 WS: Now (100 MHz-500µA/MHz) RX200 (120 MHz-300µA/MHz) (240 MHz) (50 MHz-150µA/MHz) MP: Now Low power, Performance Up to 1MB Flash and 96kB RAM MP: Now NEW NEW Ultra Low power Up to 512KB MP: Now RX100 (32 MHz-110µA/MHz)

5. 32bit MCU w/Low Power Consumption & High Performance Concept of RX200 Series- RX200 Series Overview High performance 32bit RX CPU 1.56DMISP/MHz Low power consumption 0.2mA/MHz Low voltage 1.62V to 5.5V Safety function IEC60730compliant In addition to industrial application, wide range from 1.8V portable device to 5V home appliance supported Enhance safety function of home appliance This CPU realizes lower power consumption by intermittent operation Long battery life Major applications of RX200 series [Home appliance] • Air conditioner • Refrigerator • Washing machine [Consumer] (operated by battery) • Smartphone • DSC/DVC [Healthcare] • Blood pressure meter • Glucose meter [Industrial] • Power meter • Pressure/temperature/ flow meter • Inverter

6. Compatibility between RX210and RX220 even RX600 series Complete compatibility between RX210and RX220! Drop-in replacement is available RX210 RX220 RX600

7. Starter Kit Supports from Phase of Considering Introduction to Phase of Full-scale Development All you need for MCU evaluation and initial phase of introduction is this starter kit! CPU board, emulator (E1), Integrated Development Environment (GUI), various sample codes for MCU peripherals Sample programs of middleware on the website are ready to use! Full-scale development is possible! Code with its operation checked is used for an actual system Bundled emulator is used for an actual system

8. E1 offers a wide range of basic functions at a low price! Major Renesas MCU are supported. Available as Flash programmer as well. On-chip trace function is supported for some MCUs. Renesas On-chip Debugging Emulator Meets Customer’s Needs E1

9. Environment of Flash ROM Programming: Software Succeeding software of FDT is downloadable for free! Renesas Flash Programmer New integrated Flash programming software by Renesas (Easy accessible. Suitable for development and prototype.) E1, E20 (Only E1 for RX100 series) START USB RS-232C Simple GUI specific to programming User’s system Supporting the following families:

10. RSK + E1 Check your hardware connection before debugging.

11. How to read RX datasheet There are total 42 chapters in RX210 datasheet. The description of each module is the same. Take MTU for example:

12. How to read RX datasheet There are total 42 chapters in RX210 datasheet. The description of each module is the same. Such as:

13. How to read RX datasheet There are total 42 chapters in RX210 datasheet. The description of each module is the same. Take MTU for example:

14. RX210 Core Properties RX210 Core

15. Efficient Addressing Modes RX210 Core (cont.)

16. Reduced Code Size

17. Pipelining • Pipelining is an important technique used to make fast CPUs • A pipeline consists of several stages which allows the instruction throughput to increase • A pipeline stage cannot be any faster than the slowest stage • If for example the execution stage takes more time than the memory access stage, then performance degrades to the slowest stage • The RX CPU is based on a five-stage pipeline: • Instruction Fetch Stage (IF Stage): • CPU fetches 32/64 bit instructions from the memory. • PC is incremented by 4 or 8 since the instructions are 4 or 8 bytes long • Instruction Decode Stage (ID Stage): • Instructions are decoded and converted into micro- operations.

18. Pipelining (cont.) • Execution Stage (E Stage): • Two types of calculations take place in this stage • Normal ALU operations: • – Add, sub, compare, and logical operations • Memory address calculations • Memory Access (M Stage): • Memory is accessed for either fetching an operand from the memory or storing an operand in the memory. • Write-back stage (WB stage): • The last stage of the pipeline writes data into the register file

19. The RX CPU instruction is converted into one or more micro-operations, which are then executed in pipeline processing Pipelining (cont.)

20. Converted into a basic single micro-operation Converted into multiple basic micro-operations Pipelining (cont.)

21. Fast Interrupt Response

22. RX210 Registers

23. RX210 Registers (cont.) • Sixteen general-purpose registers (R0 to R15) • R1 to R15 can be used as data registers or address registers • R0 also functions as the stack pointer (SP) • The nine control registers are: • Interrupt stack pointer (ISP)/User stack pointer (USP) • Holds the value zero after a reset • 32 bits • The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) • By the value of the stack pointer select bit (U) in the PSW • Interrupt table register (INTB) • Points to the address of the relocatable vector table • Program counter (PC) • Points to the address of the instruction that will be executed next

24. RX210 Registers (cont.) • Processor status word (PSW) • Indicates the status of the processor instruction execution or the state of the CPU, e.g.: • Result is negative, result is zero, overflow has occurred etc. • The IPL[3:0] bits specify the processor interrupt priority level • When the priority level of a requested interrupt is higher than the processor interrupt priority level, the interrupt is enabled • Backup PC (BPC) • Speeds up the response of interrupts • Backs up the program counter • Backup PSW (BPSW) • After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in this register • Fast interrupt vector register (FINTV) • As soon as a fast interrupt is generated, the FINTV register specifies a branch destination address

26. RX210 Registers (cont.) • The accumulator (ACC) is a 64-bit register used for DSP instructions • The ACC is also used for the multiply and multiply-and-accumulate instructions • The prior value in the accumulator is modified by execution of the instruction • Floating-point status word (FPSW) • Indicates the result of floating-point operations

27. Processor Mode • The RX CPU supports two processor modes • Supervisor and user • Enable the realization of a hierarchical CPU resource protection • Each processor mode imposes a level on rights of access to the CPU resources and the instructions that can be executed • Supervisor mode carries greater rights than those of user mode • The initial state after a reset is supervisor mode • In supervisor mode, all CPU resources are accessible and all instructions are available • In user mode, write access to the CPU resources listed below is restricted • Some bits (bits IPL[3:0], PM, U, and I) in the PSW • Interrupt stack pointer (ISP) & Interrupt table register (INTB) • Backup PSW (BPSW) & Backup PC (BPC) • Fast interrupt vector register (FINTV)

28. Processor Mode (cont.) • Manipulating the processor mode select bit (PM) in the processor status word (PSW) switches the processor mode • Switching from user mode to supervisor mode • After an exception has been generated, the PSW.PM bit is set to 0 and the CPU switches to supervisor mode • The hardware pre-processing is executed in supervisor mode • The state of the processor mode before the exception was generated is saved on the stack • Switching from supervisor mode to user mode • Executing an RTE instruction when the value of the copy of the PSW.PM bit that has been preserved on the stack is 1 • Executing an RTFI instruction when the value of the copy of the PSW.PM bit that has been preserved in the BPSW is 1 • The value of the stack pointer designation bit (the U bit in the PSW) becomes 1

29. DataTypes • TheRXCPUsupportssixtypesofdata: • Integer: • – 8-,16-,or 32-bit • – SignedorUnsigned

30. Endianness • Endianness refers to the arrangement of sub-units such as bytes within a longer data word, while storing it in memory • Big endian: The most significant byte (MSB) is stored at the lowest byte address of the memory. • Little endian: The least significant byte (LSB) is stored at the lowest address of the memory • The RX210 supports both big and little endian

31. DataArrangement • Data Arrangement in Registers • The least significant bit is the rightmost bit while the most significant bit is the leftmost bit

32. Data Arrangement (cont.) • DataArrangementinMemory • Byte(8-bit),word (16-bit),orlongword (32-bit) • Differentdependingon whether littleor bigendian is used

33. RX210 Interrupt Vector Table Fixed Vector Table (System) Relocatable Vector Table (Peripheral) Vector numbers (from 0 to 255) are allocated to interrupt requests in a fixed way for each product

34. DescriptionofBuses • CPU Buses • Fetches instructions for the CPU and accesses operands • Programming and erasure is handled by the internal peripheral bus • Bus-access operations can proceed simultaneously, e.g. parallel access to on-chip RAM or ROM • Memory bus • Accesses on-chip ROM and RAM • Internal main bus • Internal main bus 1 is used by the CPU • Iinternal main bus 2 is used by other bus-master modules, e.g., DTC, DMACA, and EDMAC • Bus master priority:

35. Description of Buses (cont.) • Internal peripheral bus • The table below lists the six internal peripheral buses and what peripheral modules they are connected to

36. Description of Buses (cont.) • External Bus • Arbitrates requests from the internal main bus 1, 2 and EXDMAC and decides the master • The order of priority is, from high to low: • EXDMAC • Internal main bus 2 • Internal main bus 1 • Bus Error Monitor Section • Generates an interrupt whenever an error is detected on the bus • Some errors are: • Illegal address access error • Access to areas for which operation has been disabled • Timeout error • Happens after 768 cycles if the bus access is not completed

37. RX210 Bus Configuration CPU • DTC : RAM  SFR • DMA: on-chip memory external memory • Introduction/Operand bus : CPU  ROM/RAM • Internal main bus ½ : CPU/ROM/RAM  Peripheral Introduction bus Operand bus Bus Monitor ROM RAM DTC DMA Peripheral module DTC DMA Peripheral module Peripheral module

38. RX210 Bus Configuration (cont.)

39. RX210 Peripherals

40. RX210 Peripherals (cont.) • Clock Generation Circuit: • The clock generation circuit consists of two circuits; a main clock oscillator and a sub clock oscillator. • The system clock (ICLK) operates at up to 50 MHz • The peripheral clock (PCLK) and external bus clock (BCLK) operate at up to 32 MHz and 12.5 MHz, respectively • Reset: • There are various reset sources available such as: pin reset, power-on reset, watchdog timer reset, and deep software standby reset • Voltage detection circuit: • When the voltage available on VCC falls below the voltage detection level (Vdet), an internal reset or internal interrupt is generated

41. RX210 Peripherals (cont.) • External bus extension: • The external address space is divided into nine areas: CS0 to CS7 and SDCS • A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area • Each area is specifiable as an 8-, 16-, or 32-bit bus space • Direct Memory Access (DMA): • The DMA system consists of three different controllers • DMA controller: Has four channels and three transfer modes; normal transfer, repeat transfer, and block transfer • EXDMA controller: Has two channels and four transfer modes; normal transfer, repeat transfer, block transfer, and cluster transfer • Data transfer controller: Has three transfer modes; normal transfer, repeat transfer, and block transfer

42. RX210 Peripherals (cont.) • I/O ports: • The main modules of I/O ports are programmable I/O ports • The number of programmable I/O ports depends on the package • Timers: • Seven timers are available for the controlling the sequence of events or processes • Watchdog timer (14 bits) • 8-bit timers • Compare-match timer (16 bits) • Communication function: • Controllers used for communicating with the outside world • Ethernet controller (10 or 100 Mbps) • USB 2.0 host/function module (USB 2.0, up to 12 Mbps) • Serial communication interfaces (13 channels) • I2C bus interfaces (up to 1 Mbps)

43. RX210 Peripherals (cont.) • A/D converter: • 12-bit or 10-bit • Single scan mode and continuous scan mode • D/A converter: • Two channels, 10-bit resolution • CRC calculator: • Generates code for data in 8-bit units • Low power consumption: • Four low power consumption modes are available • sleep mode, all-module clock stop mode, software standby mode and deep software standby mode • Interrupt: • 187 peripheral function interrupts are available • 16 external interrupts pins (IRQ0 to IRQ15) • 16 levels of interrupt priority can be specified

44. RX210 Peripherals (cont.) • Temperature sensor: • On-chip temperature sensor with 1 channel • Precision of 1ºC • Data encryption unit: • AES encryption and decryption functions • 128/192/256-bit key lengths • Central Processing Unit: • A 32-bit RX CPU with maximum operating frequency of 50MHz • Memory: • ROM: RX210 variants have the following ROM capacities: 64 Kbytes, 128 Kbytes, 256 Kbytes, 384 Kbytes, 512 Kbytes, 768 Kbytes, 1Mbyte • RAM: Its variants have the following capacities: 12 Kbytes, 20 Kbytes, 32 Kbytes, 64 Kbytes , 96 Kbytes • E2 Data Flash: Its capacity is 8 Kbytes

45. I/O Ports • The I/O ports function as a general I/O port • Some of the pins are also configurable as an I/O pin of a peripheral module or an input pin for an interrupt • All pins function as input pins immediately after a reset • Pin functions are switched by register settings • The setting of each pin is specified by the registers for the corresponding I/O port and on-chip peripheral modules • Each port has: • The port direction register (PDR) selects input or output direction • The port output data register (PODR) holds data for output • The port input data register (PIDR) indicates the pin states • The open drain control register y (ODRy, y = 0, 1) selects the output type of each pin • The pull-up control register (PCR) controls on/off of the input pull-up MOS

46. I/O Ports (cont.) • The driving ability control register (DSCR) selects the driving ability • The port mode register (PMR) specifies the pin function of each port

47. I/O Ports (cont.)

48. Register Description • Port Direction Register (PDR) • Used to select the input or output direction for individual pins of the corresponding port m when the pins are configured as the general I/O pins

49. PortDirectionRegister(PDR) • This register, as the name suggests, is used to set the data direction (input or output) of a pin • Each bit of the Port Direction Register represents a pin • Set the corresponding bit to 0 to make it input and set the bit to 1 to make it an output pin • Example: Setting Port 4 bit 1 as output • PORT4.PDR.BIT.B1 = 1;

50. Register Description (cont.) • Port Output Data Register (PODR) • Holds the data to be output from the pins used for general output ports