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Testing HCN for PRAM

Explore testing of Hierarchical Caching Network for PRAM, combining model checking & abstraction. Verify network behavior using abstraction and model checking techniques. Discussion on error handling, results, and program states.

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Testing HCN for PRAM

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  1. Testing HCN for PRAM Michael Jones, Ganesh Gopalakrishnan University of Utah, School of Computing

  2. Outline • Goals: • re-use an abstraction for branching topologies • combine test model checking and abstraction • How HCN works • What was verified and how • Discussion

  3. HCN • Directory-based hierarchical caching netw. • Obeys sequential consistency, and PRAM is weaker than SC. • Written by Arvind and Xiaowei Shen

  4. P P P P P M M M M P M M M M M HCN Model

  5. HCN Model P P P P wr_req (a,2) ex-req(a) P M M M M2 P M M M M1 M0

  6. HCN Model P P P P wr_req (a,2) ex-req(a) P M M M M2 P M ex-req(a) M M M1 M0

  7. Testing for PRAM • Any 3 processors • Located anywhere in any HCN network • Sharing a single address • Always satisfy PRAM • Abstraction to cover all networks • Test model check for PRAM with N=3.

  8. Testing for PRAM • # Procs sharing address: 3 • # Procs in system: arbitrary • # Caches in system: arbitrary • # Addresses being shared 1 • # Addresses in system arbitrary • Property mem model

  9. Abstraction Recipe • Throw away enough transactions and structure, and... • Merge enough structure to get a finite state model. • Add enough non-determinism to get same behavior on remaining observed state (Inspired by trace inclusion refinement)

  10. Why the Recipe Works For some class of protocols, a “nice amount” of non-determinism is required to capture all behaviors of the observed state in the reduced model

  11. HCN Abstraction M M M M2 M M M M1 M0

  12. HCN Abstraction P Q M M M M2 M P M M M1 M0

  13. HCN Abstraction P Q M M M M2 M P M M M1 M0

  14. HCN Abstraction P Q M M P M M1 M0

  15. ... ... M M ... ... M ... ... Merging Linear State ... ... ... ... ...

  16. HCN Abstraction P Q P P Q M M P M M1 M0

  17. |{Finite State Configs}| is Finite P P Q P Q P P P Q

  18. Modeling a TRS in Mur receive-wb-rep-and-send-sh-rep <id,Cell(a,u,(Ex,W(idk)))|m, Msg(idk,id,Wbrep,a,v)+i,o, Trec(a,(idp,Sh-req))|t>  <id,Cell(a,v,(Ex,R(idk|idj)))|m, i,o+Msg(id,idj,sh-rep,a,v), t> Rule "receive wb rep and send sh rep" (trec[addr].req = sh_req & hd_in.opc = wb_rep & hd_in.addr = addr & state[addr] = ex_w & (current_writer(addr,m) = hd_in.src)) ==> var rep_msg : tMsg ; begin rep_msg.opc := sh_rep; rep_msg.src := m; rep_msg.dst := trec[addr].id; rep_msg.addr := addr; rep_msg.data := hd_in.data; enqueue (outq, rep_msg); state[addr] := ex_r; add_to_dir (addr, trec[addr].id, m, dir); add_to_dir (addr, hd_in.src, m, dir); clearTrec (addr,trec); delete (inq, 0); end;

  19. rd(A,1) rd(A,-) wr(A,0) rd(A,0) wr(A,1) E wr(A,2) E rd(A,-) rd(A,1) rd(A,0) rd(A,1) rd(A,-) wr(A,1) rd(A,-) wr(A,1) rd(A,0) rd(A,-) wr(A,2) Testing for PRAM Model Checker

  20. Inadvertantly Seeded Error

  21. Model Checking Results States CPU time (sec) P P Q 110,995 87.57 P Q P 151,598 65.51 P P Q 618,874 282.40 Total 881,467 435.48

  22. Discussion •  at least one error in which topology matters • Abstraction carried over nicely to a non-PCI protocol. • N=4 and 2 addresses: both too big. • only explore several million states per model • Abstraction + test model checking = more general results.

  23. Inadvertantly Seeded Error read&miss sh-req

  24. Inadvertantly Seeded Error read&miss write&miss sh-req ex-req

  25. Inadvertantly Seeded Error read&miss write&miss write&miss sh-req ex-req ex-req

  26. Inadvertantly Seeded Error read&miss write&miss write&miss 1 2 0 sh-req ex-req ex-req ex-req(2)

  27. Inadvertantly Seeded Error read&miss write&miss write&miss 1 2:0 0 sh-req ex-req ex-rep

  28. Inadvertantly Seeded Error read&miss write&miss write&miss 1 2:0 0 sh-req ex-req wb-req ex-req(1)

  29. Cache State Encoding M State Address Value Cache Home cell cell cell ... cell

  30. Cache State Encoding “Cstate”: Shared or exclusive wrt siblings “Horizontal” state Sh = shared with siblings Ex = has an exclusive copy. State Address Value Cache Home cell cell cell ... cell

  31. Cache State Encoding “Hstate”: Which children have cached the state and why “Vertical” state R(dir) = all children in dir have shared copies for reading W(id) = the child id has an exclusive copy for writting State Address Value Cache Home cell cell cell ... cell

  32. P P P P P M M M M2 P M M M M1 M0 HCN Model M1 is a child of M0, so M1 is a cache for data in M0.

  33. HCN Model P P P P P M M M M2 P M M M M1 M1 is the parent of M2, so M1 is the home of data in M2 M0

  34. P P P P P M M M M P M M M M M HCN Model Innermost memories, or L1 caches.

  35. P P P P P M M M M P M M M M M HCN Model Outermost memory

  36. rd(A,1) rd(A,-) wr(A,0) rd(A,0) wr(A,1) E wr(A,2) E rd(A,-) rd(A,1) rd(A,0) rd(A,1) rd(A,-) wr(A,1) rd(A,-) wr(A,1) rd(A,0) rd(A,-) wr(A,2) Testing for PRAM

  37. HCN Model P P P P wr_req (a,2) ex-req(a) P M M M M2 P M ex-req(a) M M M1 wb-req(a) M0

  38. HCN Model P P P P wr_req (a,2) ex-req(a) P M M M M2 P M ex-req(a) M M M1 wb-req(a) M0

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