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PROGRAMMABLE LOGIC DESIGN WITH VHDL

PROGRAMMABLE LOGIC DESIGN WITH VHDL. Objectives. Upon completion of this training, your VHDL knowledge will enable you to: Implement efficient combinatorial and sequential logic Design state machines and understand implementation trade-offs Use hierarchy / Create reusable components

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PROGRAMMABLE LOGIC DESIGN WITH VHDL

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  1. PROGRAMMABLE LOGIC DESIGN WITH VHDL

  2. Objectives • Upon completion of this training, your VHDL knowledge will enable you to: • Implement efficient combinatorial and sequential logic • Design state machines and understand implementation trade-offs • Use hierarchy / Create reusable components • Identify how VHDL will synthesize and fit into a PLD or CPLD

  3. Introduction, Why Use VHDL? PLD Design Flow VHDL Design Descriptions The Entity, Ports, Modes, Types Exercise #1 The Architecture, Architecture Styles VHDL Statements, Combinational Logic Processes, Signals vs. Variables VHDL Operators/Overloading/Inferencing Tri-State Logic, Don't Cares VHDL Identifiers Exercise #2, Exercise #3 Registers/Sequential Logic Wait Statement, Implicit Memory Exercise #4 - Lunch State Machines and State Encoding Exercise #5 Hierarchy (components, packages, and libraries) Exercise #6 Generate Statement Multiplexing I/O pins Exercise #7 Attributes, Miscellaneous Topics, Wrap-up Agenda

  4. Introduction • VHDL is used to: • document circuits • simulate circuits • synthesize design descriptions • Synthesis is the reduction of a design description to a lower-level representation (such as a netlist or a set of equations). • This training course covers VHDL for PLD synthesis • The course will at times draw upon the concepts of VHDL as a simulation language

  5. Why Use VHDL? • Quick Time-to-Market • Allows designers to quickly develop designs requiring tens of thousands of logic gates • Provides powerful high-level constructs for describing complex logic • Supports modular design methodology and multiple levels of hierarchy • One language for design and simulation • Allows creation of device-independent designs that are portable to multiple vendors. • Allows user to pick any synthesis tool, vendor, or device

  6. PLD Design Flow • Design Entry • Schematic Capture/HDL or Both • Front-End Simulation (optional) • Design Compilation • Synthesis, Fitting/Place&Route • Design Verification • Back-End Simulation (optional) • Device Programming

  7. Design Entry Schematic Text Simulation Synthesis Design Compilation Fitting Place&Route Sim. Model Design Verification JEDEC File Prog. File Simulation Programmer Front End Back End

  8. VHDL Design Descriptions • VHDL design descriptions (referred to as "design entities") consist of an ENTITY declaration and ARCHITECTURE bodypair • The ENTITY declaration describes the design I/O • The ARCHITECTURE body describes the content of the design

  9. VHDL Entity/Architecture Pairs:2-Input And Function ENTITY and2 IS PORT ( a,b : IN std_logic; f: OUT std_logic); END and2; ARCHITECTURE behavioral OF and2 IS BEGIN f <= a AND b; END behavioral;

  10. The Entity • A “BLACK BOX” • The ENTITY describes the periphery of the black box (i.e., the design I/O) BLACK_BOX rst q[7:0] d[7:0] co clk

  11. BLACK_BOX rst q[7:0] d[7:0] co clk Example Entity declaration ENTITY black_box IS PORT ( clk, rst: INstd_logic; d: INstd_logic_vector(7 DOWNTO 0); q: OUTstd_logic_vector(7 DOWNTO 0); co: OUTstd_logic); END black_box; • More shortly

  12. The Entity Declaration ENTITYentity_name IS PORT ( -- optional generics name : mode type ; ... ) ; ENDentity_name; • entity_name is an arbitrary name • generics are used for defining paramaterized components • name is the signal/port identifier and may be a comma separate list for ports of identical modes and types • mode describes the direction the data is flowing • type indicates the set of values the port name may be assigned

  13. Ports • The Entity (“BLACK BOX”) has PORTS • PORTS are points of communication • PORTS are often associated with the device pins • PORTS are a special class of SIGNAL • PORTS have an associated SIGNAL name,mode, and type

  14. PORT modes A port’s MODE is the direction data is transferred: • IN Data goes into the entity but not out • OUT Data goes out of the entity but not in (and is not used internally) • INOUT Data is bi-directional (goes into and out of the entity) • BUFFER Data that goes out of the entity and is also fed-back internally within the entity

  15. IEEE 1076 Types • VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type) • bit - a signal of type bit that can only take values of '0' or '1' • bit_vector - a grouping of bits (each can be '0' or '1') SIGNAL a: BIT_VECTOR(0 TO 3); -- ascending range SIGNAL b: BIT_VECTOR(3 DOWNTO 0); -- descending range a <= "0111"; -- double quotes used for vectors b <= "0101"; This means that: a(0) = '0' b(0) = '1' a(1) = '1' b(1) = '0' a(2) = '1' b(2) = '1' a(3) = '1' b(3) = '0'

  16. IEEE 1076 TYPES (contd.) • INTEGER • useful as index holders for loops, constants, generics, or high-level modeling • BOOLEAN • can take values ‘TRUE’ or ‘FALSE’ • ENUMERATED • has user defined set of possible values, e.g., • TYPE states IS (start, slow, fast, stop);

  17. IEEE 1164 • "Multi-value logic system for VHDL interoperability" • A package created as an aid to VHDL users • Nine values as opposed to two ('0' and '1') • Allows increased flexibility in behavioral VHDL coding, synthesis, and simulation • std_logic and std_logic_vector are used as opposed to bit and bit_vector when a multi-valued logic system is required. • std_logic and std_logic_vector are used when tri-state logic is required.

  18. 1164 Types • std_logic and std_logic_vector are the industry standard logic type for digital design • All 9 values are valid in a VHDL simulator, however only: • ‘0’ -- Forcing ‘0’ • ‘1’ -- Forcing ‘1’ • ‘Z’ -- High Impedance • ‘L’ -- Weak ‘0’ • ‘H’ -- Weak ‘1’ • ‘-’ -- Don’t care are recognized for logic synthesis

  19. BLACK_BOX MODE rst TYPE q[7:0] d[7:0] co clk Entity Declaration Example LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY black_box IS PORT ( clk, rst: INstd_logic; d: INstd_logic_vector(7 DOWNTO 0); q: OUTstd_logic_vector(7 DOWNTO 0); co: OUTstd_logic); END black_box;

  20. Exercise #1: The Entity • Write an entity declaration for the following: Port D is a 12-bit bus, input only Port OE and CLK are each input bits Port AD is a 12-bit, three-state bi-directional bus Port A is a 12-bit bus, output only Port INT is a three-state output Port AS is an output also used internally my_design ad[11:0] d[11:0] a[11:0] oe int clk as

  21. my_design ad[11:0] d[11:0] a[11:0] oe int clk as Exercise #1: Solution LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY my_design IS PORT ( d: IN std_logic_vector(11 DOWNTO 0); oe, clk: IN std_logic; ad: INOUT std_logic_vector(11 DOWNTO 0); a: OUT std_logic_vector(11 DOWNTO 0); int: OUT std_logic; as: BUFFER std_logic); END my_design; -- In this presentation, VHDL keywords -- are highlighted in bold, CAPITALS; -- however, VHDL is not case sensitive: -- clock, Clock, CLOCK all refer to the -- same signal, -- means a comment

  22. The Architecture • Architectures describe what is in the black box (i.e., the structure or behavior of entities) • Descriptions can be either a combination of • Structural descriptions • Instantiations (placements of logic-much like in a schematic-and their connections) of building blocks referred to as components • Behavioral/Dataflow descriptions • Algorithmic (or “high-level”) descriptions: IF a = b THEN state <= state5; • Boolean equations (also referred to as dataflow): x <= (a OR b) AND c;

  23. The Architecture Declaration ARCHITECTURE arch_name OFentity_name IS -- optional signal declarations, etc. BEGIN --VHDL statements ENDarch_name; • arch_name is an arbitrary name • optional signal declarations are used for signals local to the architecture body (that is, not the entity’s I/O). • entity_name is the entity name • statements describe the function or contents of the entity

  24. Architecture Body Styles : Behavioral ENTITY compare ISPORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; ARCHITECTURE behavior OF compare IS BEGIN comp: PROCESS (a,b) BEGIN IF a = b THEN equals <= '1' ; ELSE equals <= '0' ; ENDIF ; ENDPROCESS comp; END behavior;

  25. Architecture Body Styles : Dataflow ENTITY compare ISPORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; ARCHITECTURE dataflow OF compare IS BEGIN equals <= '1' WHEN a = b ELSE '0' ; END dataflow;

  26. Architecture Body Styles : Structural ENTITY compare ISPORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; USEWORK.gatespkg.ALL ; ARCHITECTURE structure OF compare IS SIGNAL x : std_logic_vector (0 to 3) ; BEGIN u0: xnor2 PORTMAP (a(0),b(0),x(0)) ; u1: xnor2 PORTMAP (a(1),b(1),x(1)) ; u2: xnor2 PORTMAP (a(2),b(2),x(2)) ; u3: xnor2 PORTMAP (a(3),b(3),x(3)) ; u4: and4 PORTMAP (x(0),x(1),x(2),x(3),equals) ; END structure;

  27. Comparing Architecture Styles • These examples synthesize to equivalent circuits • In more elaborate designs, some descriptions may yield more efficient circuits • sloppy code = inefficient results (see section 3.3.4) • Use styles that make your designs easier to describe and maintain • Behavioral/Dataflow exploit module generation (described later) • Structural descriptions may make the design less portable (may rely on a library of vendor-specific components)

  28. LOGIC a d b f c Mixing Architecture Styles • The various styles may be mixed in one architecture. ENTITY logic IS PORT ( a,b,c: IN std_logic; f: OUT std_logic); END logic; USE WORK.gatespkg.ALL; ARCHITECTURE archlogic OF logic IS SIGNAL d: std_logic; BEGIN d <= a AND b; g1: nor2 PORT MAP (c, d, f); END archlogic; g1 Behavioral/Dataflow Structural

  29. VHDL Statements • There are two types of statements • Sequential • Though hardware is concurrent, it may be modeled with algorithms, by a series of sequential statements • By definition, sequential statements are grouped using a process statement. • Concurrent • Statements outside of a process are evaluated concurrentlyduring simulation • Processes are concurrent statements

  30. Concurrent Statements • Concurrent statements include: • boolean equations • conditional/selective signal assignments (when/else, with/select) • instantiations • Examples of concurrent statements: -- Examples of boolean equations x <= (a AND (NOT sel1)) OR (b AND sel1); g <= NOT (y AND sel2); -- Examples of conditional assignments y <= d WHEN (sel1 = '1') ELSE c; h <= '0' WHEN (x = '1' AND sel2 = '0') ELSE '1'; -- Examples of instantiation inst: nand2 PORT MAP (h, g, f);

  31. The Process Statement • Used to construct algorithms/group sequential statements • Statements within a process are sequential statements-they execute sequentially during simulation • An architecture can contain multiple processes. Each process is executed concurrently • Processes may be used to model combinational or synchronous logic

  32. The Process (contd.) label: PROCESS (sensitivity list) -- variable declarations BEGIN -- sequential statements END PROCESS label ; • The process label and variable declarations are optional • The process executes when one of the signals in the sensitivity list has an event (changes value).

  33. Process (contd.) • Processes are executing or suspended (active or inactive/awake or asleep) • A process typically has a sensitivity list • When a signal in the sensitivity list changes value, the process is executed by the simulator • e.g., a process with a clock signal in its sensitivity list becomes active on changes of the clock signal • All signal assignments occur at the END PROCESS statement in terms of simulation • The process is then suspended until there is an event (change in value) on a signal in the sensitivity list

  34. Combinational Logic • Can be described with concurrent statements • e.g. with-select-when, when-else, boolean equations, component instantiatons • Can be described with sequential statements • e.g. if-then-else, case-when

  35. Combinational Logic w/ Boolean Equations • Boolean Equations can be used in both concurrent and sequential signal assignment statements. • A 4-1 multiplexer is shown below x <= (a AND NOT(s(1)) AND NOT(s(0))) OR (b AND NOT(s(1)) AND s(0)) OR (c AND s(1) AND NOT(s(0))) OR (d AND s(1) AND s(0)) ; s 2 a x b mux c d

  36. Selective Signal Assignment:with-select-when • Assignment based on a selection signal • WHEN clauses must be mutually exclusive • Use a WHEN OTHERS to avoid latches • Only one reference to the signal, only one assignment operator (<=) WITH selection_signal SELECT signal_name <= value_1 WHEN value_1 of selection_signal, value_2 WHEN value_2 of selection_signal, ... value_n WHEN value_n of selection_signal, value_x WHEN OTHERS;

  37. Combinational Logic w/ Selective Signal Assignment • The same 4-1 multiplexer is shown below with s select x <= a when “00” , b when “01” , c when “10” , d whenothers ;

  38. More on with-select-when • You can use a range of values with int_value select x <= a when 0 to 3, b when 4 | 6 | 8 , c when 10 , d whenothers ;

  39. Conditional Signal Assignment:when-else • Signal is assigned a value based on conditions • Any simple expression can be a condition • Priority goes in order of appearance • Only one reference to the signal, only one assignment operator (<=) • Use a final ELSE to avoid latches signal_name <= value_1 WHEN condition1 ELSE value_2 WHEN condition2 ELSE ... value_n WHEN conditionn ELSE value_x ;

  40. Combinational Logic w/ Conditional Signal Assignment • The same 4-1 multiplexer is shown below x <= a when (s = “00”) else b when (s = “01”) else c when (s = “10”) else d ;

  41. Combinational Logic w/ Conditional Signal Assignment • The when conditions do not have to be mutually exclusive (as in with-select-when) • A priority encoder is shown below j <= w when (a = ‘1’) else x when (b = ‘1’) else y when (c = ‘1’) else z when (d = ‘1’) else ‘0’ ;

  42. Combinational Logic w/ Sequential Statements • Grouped together with Processes • Processes are concurrent with one another and with concurrent statements • Order of sequential statements does make a difference in synthesis

  43. Sequential Statementsif-then-else • Used to select a set of statements to be executed • Selection based on a boolean evaluation of a condition or set of conditions IF condition(s) THEN do something; ELSIF condition_2 THEN -- optional do something different; ELSE -- optional do something completely different; END IF ;

  44. if-then-else • Absence of ELSE results in implicit memory • 4-1 mux shown below mux4_1: process (a, b, c, d, s) begin if s = “00” then x <= a ; elsif s = “01” then x <= b ; elsif s = “10” then x <= c ; else x <= d ; end process mux4_1 ;

  45. Sequentional Statements: Case-When CASE selection_signal WHEN value_1_of_selection_signal => (do something) -- set of statements 1 WHEN value_2_of_selection_signal => (do something) -- set of statements 2 ... WHEN value_N_of_selection_signal => (do something) -- set of statements N WHEN OTHERS => (do something) -- default action END CASE;

  46. The CASE Statement: 4-1 Mux ARCHITECTURE archdesign OF design IS SIGNAL s: std_logic_vector(0 TO 1); BEGIN mux4_1: PROCESS (a,b,c,d,s) BEGIN CASE s IS WHEN "00" => x <= a; WHEN "01" => x <= b; WHEN "10” => x <= c; WHEN OTHERS => x <= d; END CASE; END PROCESS mux4_1; END archdesign;

  47. s a(3 DOWNTO 0) x(3 DOWNTO 0) b(3 DOWNTO 0) Sequential Statements: An Example mux: PROCESS (a, b, s) BEGIN IF s = '0' THEN x <= a; ELSE x <= b; END IF; END PROCESS mux; • Note: logic within a process can be registered or combinatorial • Note: the order of the signals in the sensitivity list is not important • Note: the process mux is sensitive to signals a, b, and s; i.e., whenever one or more of those signals changes value, the statements inside of the process are executed

  48. a c clock Signal Assignment in ProcessesWhich Circuit is Correct? PROCESS BEGIN WAIT UNTIL clock = '1' ; -- implied sensitivity list b <= a; c <= b; END PROCESS ; b c a clock

  49. Signal Assignment in Processes (contd.) • Signals are not updated immediately. Rather, they are scheduled. • The signals are not updated until time advances (after the End Process statement) • Therefore, two registers will be synthesized • Note: In some instances, the use of concurrent statements outside the process may alleviate the problem, but this is not possible with registered logic.

  50. VARIABLES • When a concurrent signal assignment cannot be used, the previous problem can be avoided using a VARIABLE • Variables can only exist within a PROCESS, they cannot be used to communicate information between processes • Variables can be of any valid data type • The value assigned to a variable is available immediately • The variable assignment statement is used to assign values to variables, e.g., c := a AND b;

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